Search Results - "Leveugle, R"

Statistical fault injection: Quantified error and confidence by Leveugle, R., Calvez, A., Maistri, P., Vanhauwaert, P.

“…Fault injection has become a very classical method to determine the dependability of an integrated system with respect to soft errors. Due to the huge number…”
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Double-Data-Rate Computation as a Countermeasure against Fault Analysis by Maistri, P., Leveugle, R.

“…Differential Fault Analysis (DFA) is one of the most powerful techniques to attack cryptosystems. Several countermeasures have been proposed, which are based…”
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CNTFET Modeling and Reconfigurable Logic-Circuit Design by O'Connor, I., Liu Junchen, Gaffiot, F., Pregaldiny, F., Lallement, C., Maneux, C., Goguet, J., Fregonese, S., Zimmer, T., Anghel, L., Trong-Trinh Dang, Leveugle, R.

“…This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET)…”
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Early Analysis of Fault-based Attack Effects in Secure Circuits by Leveugle, R.

“…Security often relies on functions implemented in hardware. But, various types of attacks have been developed, in particular, fault-based attacks allowing a…”
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Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA by Canivet, G., Maistri, P., Leveugle, R., Clédière, J., Valette, F., Renaudin, M.

“…Programmable devices are an interesting alternative when implementing embedded systems on a low-volume scale. In particular, the affordability and the…”
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Experimental Demonstration of Pattern Influence on DRAM SEU and SEFI Radiation Sensitivities by Bougerol, A, Miller, F, Guibbaud, N, Leveugle, R, Carriere, T, Buard, N

“…Thanks to laser and accelerator tests, we investigated the influence of test patterns regarding both SEU and SEFI radiation sensitivities for several DRAM…”
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Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic by Monnet, Y., Renaudin, M., Leveugle, R.

“…This paper presents hardening techniques against fault attacks and the practical evaluation of their efficiency. The circuit technology investigated to improve…”
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Microprocessor Soft Error Rate Prediction Based on Cache Memory Analysis by Houssany, S., Guibbaud, N., Bougerol, A., Leveugle, R., Miller, F., Buard, N.

“…Static raw soft-error rates (SER) of COTS microprocessors are classically obtained with particle accelerators, but they are far larger than real application…”
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Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems by Bergaoui, S., Wecxsteen, A., Leveugle, R.

“…Several criteria can be used to evaluate the criticality of registers and memory locations at compile time. This evaluation is useful to guide optimizations…”
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Using run-time reconfiguration for fault injection applications by Antoni, L., Leveugle, R., Feher, B.

“…The probability of faults occurring in the field increases with the evolution of the CMOS technologies. It becomes, therefore, increasingly important to…”
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A Highly Flexible Hardened RTL Processor Core Based on LEON2 by Portolan, M., Leveugle, R.

“…We present a hardened RTL processor core based on Leon2. Modifications are done at RT-level to achieve high configurability in an early stage of the…”
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Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments by Leveugle, R, Hadjiat, K

“…Issue Title: Special Issue on the Eighth IEEE International On-Line Testing Workshop (IOLTW'02) The probability of transient faults increases with the…”
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Configuration errors analysis in SRAM-based FPGAs: Software tool and practical results by Maingot, V., Ferron, J.B., Leveugle, R., Pouget, V., Douin, A.

“…The reconfigurability of SRAM-based FPGAs has also some drawbacks, especially when used in systems requiring a high level of safety and/or dependability…”
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Fault injection in VHDL descriptions and emulation by Leveugle, R.

“…Analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of faults. It…”
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Secure Test with RSNs: Seamless Authenticated Extended Confidentiality by Maistri, P., Reynaud, V., Portolan, M., Leveugle, R.

“…The testability of electronic devices is of critical importance and it is often supported by IEEE standards. The presence of test structures, on the other…”
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Early SEU fault injection in digital, analog and mixed signal circuits: a global flow by Leveugle, R., Ammari, A.

“…Fault injection techniques have been proposed for years to early analyze the dependability characteristics of digital circuits. Very few attempts have however…”
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Asynchronous circuits transient faults sensitivity evaluation by Monnet, Y., Renaudin, M., Leveugle, R.

“…This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture,…”
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Automatic modifications of high level VHDL descriptions for fault detection or tolerance by Leveugle, R.

“…The need for integrated mechanisms providing on-line error detection or fault tolerance is becoming a major concern due to the increasing sensitivity of the…”
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Using run-time reconfiguration for fault injection in hardware prototypes by Antoni, L., Leveugle, R., Feher, M.

“…In this paper, a new methodology for the injection of single event upsets (SEU) in memory elements is introduced. SEUs in memory elements can occur due to many…”
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Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation by Ammari, A, Hadjiat, K, Leveugle, R

“…Issue Title: Special Issue on On-Line-Testing and Fault Tolerance Several approaches have been proposed to early analyze the functional impact of a set of…”
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