Search Results - "Leenstra, J"

The microarchitecture of the synergistic processor for a cell processor by Flachs, B., Asano, S., Dhong, S.H., Hofstee, H.P., Gervais, G., Roy Kim, Le, T., Peichun Liu, Leenstra, J., Liberty, J., Michael, B., Hwa-Joon Oh, Mueller, S.M., Takahashi, O., Hatakeyama, A., Watanabe, Y., Yano, N., Brokenshire, D.A., Peyravian, M., Vandung To, Iwata, E.

“…This paper describes an 11 FO4 streaming data processor in the IBM 90-nm SOI-low-k process. The dual-issue, four-way SIMD processor emphasizes achievable…”
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N09C6 (Alliance) - A Phase 3, Randomized Double-Blind Study of Doxepin Rinse Versus Placebo in the Treatment of Acute Oral Mucositis Pain in Patients Receiving Head and Neck Radiation Therapy With or Without Chemotherapy by Miller, R.C, Leenstra, J, Qun, R, Martenson, J.A, Dornfeld, K.J, Bearden, J.D, Puri, D, Stella, P.J, Foote, R.L, Loprinzi, C.L

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A 1.8-GHz instruction window buffer for an out-of-order microprocessor core by Leenstra, J., Pille, J., Muller, A., Sauer, W.M., Sautter, R., Wendel, D.F.

“…To address the challenges in microprocessor designs beyond a gigahertz, an instruction window buffer (IWB) was designed. The IWB implements the processor parts…”
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A 1.8GHz instruction window buffer by Leenstra, J, Pille, J, Mueller, A, Sauer, W, Sautter, R, Wendel, D

“…Microprocessor chips were used to demonstrate the operation of the instruction window buffer (IWB) macros at 1.8GHz using 0.18 mu m CMOS8S bulk technology. The…”
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Long-Term Outcomes in Patients With Lung Metastases Treated With Ablative Radiotherapy in the Modern Era by Gits, H.C., Breen, W., Harmsen, W.S., Garces, Y., James, S.E., Jr, A.L. Stockham, Leenstra, J.L., Wilson, Z., Yu, N.Y., Rule, W.G., Ashman, J.B., Sio, T.T.W., Schild, S.E., Olivier, K., Park, S.S., Hallemeier, C.L., Merrell, K.W., Lucido, J., Owen, D.

“…Metastasis-directed radiotherapy (RT) may improve disease free and overall survival (OS) in select patients with lung metastases (LM). Long-term toxicity and…”
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Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability by Kessler, M., Kiefer, G., Leenstra, J., Schunemann, K., Schwarz, T., Wunderlich, H.-J.

“…In this paper a novel hierarchical DfT methodology is presented which is targeted to improve the delay fault testability for external testing and scan based…”
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The vector fixed point unit of the synergistic processor element of the cell architecture processor by Mading, N., Leenstra, J., Pille, J., Sautter, R., Buttner, S., Ehrenreich, S., Haller, W.

“…A vector fixed point unit (FXU) is designed to speed up multimedia processing. The FXU implements SIMD style integer arithmetic and permute operations. The…”
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POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor by Wendel, D F, Kalla, R, Warnock, J, Cargnoni, R, Chu, S G, Clabes, J G, Dreps, D, Hrusecky, D, Friedrich, J, Islam, S, Kahle, J, Leenstra, J, Mittal, G, Paredes, J, Pille, J, Restle, P J, Sinharoy, B, Smith, G, Starke, W J, Taylor, S, Van Norstrand, J, Weitzel, S, Williams, P G, Zyuban, V

“…This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz,…”
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BIST Power Reduction Using Scan-Chain Disable in the Cell Processor by Zoellin, C., Wunderlich, H.J., Maeding, N., Leenstra, J.

“…Built-in self test is a major part of the manufacturing test procedure for the cell processor. However, pseudo random patterns cause a high switching activity…”
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Hierarchical Test Program Development for Scan Testable Circuits by Leenstra, J., Spaanenburg, L.

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A streaming processing unit for a CELL processor by Flachs, B., Asano, S., Dhong, S.H., Hotstee, P., Gervais, G., Kim, R., Le, T., Liu, P., Leenstra, J., Liberty, J., Michael, B., Oh, H., Mueller, S.M., Takahashi, O., Hatakeyama, A., Watanabe, Y., Yano, N.

“…The design of a 4-way SIMD streaming data processor emphasizes achievable performance in area and power. Software controls data movement and instruction flow,…”
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Issues in the test of artificial neural networks by Warkowski, F., Leenstra, J., Nijhuis, J., Spaanenburg, L.

“…Test concepts for artificial neural networks are discussed. It is shown that the traditional design-for-test techniques such as (boundary) scan are of limited…”
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Scan chain clustering for test power reduction by Elm, Melanie, Wunderlich, Hans-Joachim, Imhof, Michael E., Zoellin, Christian G., Leenstra, Jens, Maeding, Nicolas

“…An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the…”
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A Phase III, Randomized Double-Blind Study of Doxepin Rinse versus Magic Mouthwash versus Placebo in the Treatment of Acute Oral Mucositis Pain in Patients Receiving Head and Neck Radiotherapy with or without Chemotherapy (Alliance A221304) by Miller, R.C, Le-Rademacher, J, Sio, T.T.W, Leenstra, J.L, Rine, G.P, Curtis, A, Singh, A.K, Martenson, J.A, Novotny, R.J, Tan, A.D, Reiter, P, Loprinzi, C.L

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The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor by Mading, N., Leenstra, J., Pille, J., Sautter, R., Buttner, S., Ehrenreich, S., Haller, W.

“…A vector fixed point unit (FXU) is designed to speed up multi-media processing. The FXU implements SIMD style integer arithmetic and permute operations. The…”
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Scan test planning for power reduction by Imhof, Michael E., Zoellin, Christian G., Wunderlich, Hans-Joachim, Maeding, Nicolas, Leenstra, Jens

“…Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown…”
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A 1.8 GHz Instruction Window Buffer by Leenstra, J., Pille, J., Mueler, A., Sauer, W., Sautter, R., Wendel, D.

“…An Instruction Window Buffer (IWB) addresses the challenges in microprocessor designs beyond a GHz. The IWB implements the processor parts for renaming,…”
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Hierarchical Random Simulation Approach For The Verification Of S/390 Cmos Multiprocessors by Walter, J., Leenstra, J., Dottling, G., Leppla, B., Munster, H., Kark, K., Wile, B.

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Hierarchical test assembly for macro based VLSI design by Leenstra, J., Spaanenburg, L.

“…A novel incremental procedure for the hierarchical assembly of macro test specifications into a chip test program is presented. To solve test…”
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Using hierarchy in macro cell test assembly by Leenstra, J., Spaanenburg, L.

“…Test generation and assembly are investigated for hierarchical VLSI designs of modules with testable macro cells and an associated local controller. To create…”
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