Search Results - "Lee, Taek Yeong"

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories by Park, Ki-Tae, Kang, Myounggon, Kim, Doogon, Hwang, Soon-Wook, Choi, Byung Yong, Lee, Yeong-Taek, Kim, Changhyun, Kim, Kinam

“…A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference…”
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A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency by Song, Ki-Whan, Kim, Jin-Young, Yoon, Jae-Man, Kim, Sua, Kim, Huijung, Chung, Hyun-Woo, Kim, Hyungi, Kim, Kanguk, Park, Hwan-Wook, Kang, Hyun Chul, Tak, Nam-Kyun, Park, Dukha, Kim, Woo-Seop, Lee, Yeong-Taek, Oh, Yong Chul, Jin, Gyo-Young, Yoo, Jeihwan, Park, Donggun, Oh, Kyungseok, Kim, Changhyun, Jun, Young-Hyun

“…A functional 4F 2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A…”
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A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure by PARK, Ki-Tae, KANG, Myounggon, JUNG, Soon-Moon, KIM, Changhyun, HWANG, Soonwook, KIM, Doogon, CHO, Hoosung, JEONG, Youngwook, SEO, Yong-Il, JANG, Jaehoon, KIM, Han-Soo, LEE, Yeong-Taek

“…A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with shared bitline structure have successfully developed. The device is…”
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Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories by Kang, Myounggon, Park, Ki-Tae, Song, Youngsun, Hwang, Soonwook, Choi, Byung Yong, Song, Yunheub, Lee, Yeong-Taek, Kim, Changhyun

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A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes by Cho, Taehee, Lee, Yeong-Taek, Kim, Eun-Cheol, Lee, Jin-Wook, Choi, Sunmi, Lee, Seungjae, Kim, Dong-Hwan, Han, Wook-Ghee, Lim, Young-Ho, Lee, Jae-Duk, Choi, Jung-Dal, Suh, Kang-Deog

“…A 116.7-mm/sup 2/ NAND flash memory having two modes, 1-Gb multilevel program cell (MLC) and high-performance 512-Mb single-level program cell (SLC) modes, is…”
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A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth by Youngdon Choi, Ickhyun Song, Mu-Hui Park, Hoeju Chung, Sanghoan Chang, Beakhyoung Cho, Jinyoung Kim, Younghoon Oh, Duckmin Kwon, Jung Sunwoo, Junho Shin, Yoohwan Rho, Changsoo Lee, Min Gu Kang, Jaeyun Lee, Yongjin Kwon, Soehee Kim, Jaehwan Kim, Yong-Jun Lee, Qi Wang, Sooho Cha, Sujin Ahn, Horii, Hideki, Jaewook Lee, Kisung Kim, Hansung Joo, Kwangjin Lee, Yeong-Taek Lee, Jeihwan Yoo, Jeong, G.

“…Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and…”
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A study of electromigration in 3-D flip Chip Solder joint using numerical Simulation of heat flux and current density by Lee, T.-Y.T., Taek-Yeong Lee, King-Ning Tu

“…This paper applies an analogy between heat flow and current flow to examine the current density distribution in a solder interconnect, which has a direct…”
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Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D Poisson equation by Lee, Yeong-Taek, Woo, Dong-Soo, Lee, Jong Duk, Park, Byung-Gook

“…A quasi-two-dimensional (2-D) threshold voltage reduction model for buried channel pMOSFETs is derived. In order to account for the coexistence of isoand…”
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Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory by Dae Seok Byeon, Chi-Weon Yoon, Hyun-Kook Park, Yong-Kyu Lee, Hyo-Jin Kwon, Yeong-Taek Lee, Ki-Sung Kim, Yong-Yeon Joo, In-Gyu Baek, Young-Bae Kim, Jeong-Dal Choi, Kye-Hyun Kyung, Jeong-Hyuk Choi

“…In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test…”
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Indium doped nMOSFETs and buried channel pMOSFETs with n+ polysilicon gate by LEE, Y.-T, SONG, K.-W, PARK, B.-G, LEE, J. D

“…We have investigated the properties of indium for channel doping engineering. We have fabricated 0.1 µ m super-steep-retrograde (SSR) channel nMOSFETs and…”
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Influences of particle size upon room temperature structure of BaTiO3 thin films on p-Si substrates by Min, Ki-Deuk, Lee, Jongwon, Lee, Taek Yeong, Chun, Jong Han, Lee, Hong-Kee, Kim, Dae Jung, Choi, Yong Dae, Cho, Bong Gyoo

“…The current study performed the growth of BaTiO 3 thin film on p-Si substrate by using RF-Magnetron sputtering system and the effects of thickness and particle…”
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55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure by Ki-Whan Song, Hoon Jeong, Jae-Wook Lee, Sung In Hong, Nam-Kyun Tak, Young-Tae Kim, Yong Lack Choi, Han Sung Joo, Sung Hwan Kim, Ho Ju Song, Yong Chul Oh, Woo-Seop Kim, Yeong-Taek Lee, Kyungseok Oh, Changhyun Kim

“…This paper presents a capacitor-less 1T DRAM cell transistor with high scalability and long retention time. It adopts gate to source/drain non-overlap…”
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A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond by Ki-Tae Park

“…A new page architecture with temporary LSB storing program scheme is presented as a breakthrough solution for sub-40nm FG (floating-gate) MLC NAND flash…”
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Dynamic Vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories by Park, Ki-Tae, Kang, Myounggon, Hwang, Soonwook, Song, Youngsun, Lee, Jaewook, Joo, Hansung, Oh, Hyun-Sil, Kim, Jae-ho, Lee, Yeong-taek, Kim, Changhyun, Lee, Wonseong

“…In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase cells are presented for achieving high program inhibition of sub-40nm MLC NAND flash and…”
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SCR-based ESD Protection for High Bandwidth DRAMs by Myounggon Kang, Ki-Whan Song, Hoeju Chung, Jinyoung Kim, Yeong-Taek Lee, Changhyun Kim

“…A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT)…”
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A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency by Song, Ki-Whan, Kim, Jin-Young, Kim, Huijung, Chung, Hyun-Woo, Kim, Hyungi, Kim, Kanguk, Park, Hwan-Wook, Kang, Hyun Chul, Kim, Sua, Tak, Nam-kyun, Park, Dukha, Kim, Woo-Seop, Lee, Yeong-Taek, Oh, Yong Chul, Jin, Gyo-Young, Yoo, Jeihwan, Oh, Kyungseok, Kim, Changhyun, Lee, Won-Seong

“…This paper reports a functional 4F 2 DRAM based on a vertical-channel-access-transistor (VCAT). A new core design methodology is applied to accommodate 4F 2…”
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Interfacial reactions and drop reliabilities of lead-free solder joints with electrolytic Cu metallizations by Young Kun Jee, Jong Yeon Kim, Jin Yu, Taek Yeong Lee

“…In the present work, Kirkendall void formation and drop impact reliability between Pb-free solder and Cu metallization were investigated. Pb-free solders,…”
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A comparative study of ENIG and Cu OSP surface finishes on the mechanical reliability of Sn-3.0Ag-0.5Cu and Sn-36.8Pb-0.4Ag Solders by Jee, Y.K., Sohn, Y.C., Jin Yu, Taek-Yeong Lee

“…The mechanical reliability of surface finishes ; electroless Ni(P)/Au(ENIG), Cu OSP and electrolytic Ni/Au finishes, were evaluated with Sn-3.0Ag-0.5Cu (all in…”
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A study of electromigration in 3D flip chip solder joint using numerical simulation of heat flux and current density by Lee, T.-Y.T., Taek Yeong Lee, King-Ning Tu

“…This paper applies an analogy between heat flow and current flow to examine the current density distribution in a solder interconnect, which has a direct…”
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A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency by Song, Ki-Whan, Kim, Jin-Young, Yoon, Jae-Man, Kim, Sua, Kim, Huijung, Chung, Hyun-Woo, Kim, Hyungi, Kim, Kanguk, Park, Hwan-Wook, Kang, Hyun Chul, Tak, Nam-Kyun, Park, Dukha, Kim, Woo-Seop, Lee, Yeong-Taek, Oh, Yong Chul, Jin, Gyo-Young, Yoo, Jeihwan, Park, Donggun, Oh, Kyungseok, Kim, Changhyun, Jun, Young-Hyun

“…A functional hbox 4 F 2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor…”
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