Search Results - "Leary, Glenn"

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    Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique by Leary, G., Srinivasan, K., Mehta, K., Chatha, K.S.

    “…The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the…”
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    Journal Article
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    System-Level Synthesis of Dataplane Subsystems for MPSoCs by Leary, Glenn

    Published 01-01-2013
    “…In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS…”
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    Dissertation
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    System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC by Leary, Glenn, Che, Weijia, Chatha, Karam S.

    Published in DAC Design Automation Conference 2012 (03-06-2012)
    “…Many embedded processor chips aimed at high performance and low power application domains are implemented as multiprocessor System-on-Chip (MPSoC) devices. The…”
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    Conference Proceeding
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    Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance by Leary, G., Chatha, K.S.

    “…Many SoC architectures aimed at the multimedia domain support multiple use cases where only a subset of the applications is active at any time. Further, each…”
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    Conference Proceeding
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    System-Level Synthesis of Dataplane Subsystems for MPSoCs by Leary, Glenn

    “…In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS…”
    Get full text
    Dissertation
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    A holistic approach to network-on-chip synthesis by Leary, Glenn, Chatha, Karam S.

    “…Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor…”
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    Conference Proceeding
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    Performance and resource optimization of NoC router architecture for master and slave IP cores by Leary, Glenn, Mehta, Krishna, Chatha, Karam S.

    “…System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper…”
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    Conference Proceeding