Search Results - "Le Helley, M."

FLAG: a flexible layout generator for analog MOS transistors by Mathias, H., Berger-Toussan, J., Jacquemod, G., Gaffiot, F., Le Helley, M.L.

“…This paper describes a flexible MOS transistor layout generator which draws optimal layouts whatever the W and L dimensions. The drawing methodology is based…”
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Analytical expression for the potential of guard rings of diodes operating in the punchthrough mode by Boisson, V., Le Helley, M., Chante, J.P.

“…An analytical modeling is given to prove that the potential of the floating guard ring varies linearly versus the reverse applied bias in planar punch through…”
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The problem of boundary data exchange in a hybrid computation of thermal fields in electronic equipment by Lisik, Z., Le Helley, M., Lauger, M., Podgorski, J., Kopec, M.

“…The paper describes the results of common works of the Technical University of Lodz (TUL) and the Ecole Centrale de Lyon (ECL) to give the software for 3D…”
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Computer study of a high-voltage a p-π-n--n+diode and comparison with a field-limiting ring structure by Boisson, V., Le Helley, M., Chante, J.

“…The paper presents a two-dimensional numerical analysis of a high-voltage p-π-n - -n + structure. The effect of the device parameters, such as the implanted…”
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C.A.D. OF THE PERIPHERY OF PLANAR JUNCTIONS by BOISSON, V., LE HELLEY, M., CHANTE, J.P.

“…This paper describes the algorithm used to perform numerical simulation on reverse biased planar junctions. The two-dimensional Poisson's equation is solved…”
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Computer study of a high-voltage p- pi -n super(-)-n super(+) diode and comparison with a field limiting ring structure by Boisson, V, Le Helley, M, Chante, J P

“…The paper presents a two-dimensional numerical analysis of a high-voltage p- pi -n super(-)-n super(+) structure. The effect of the device parameters, such as…”
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Experimental validation of electrothermal simulations using SETIPIC for analogue integrated circuits by Ecrabey, J., Hebrard, L., Klingeihofer, C., Gaffiot, F., Jacquemod, G., Berger-Toussan, J., Le Helley, M.

“…This paper presents the validation of SETIPIC-an electrothermal simulator for power integrated circuits. SETIPIC works by alternation of electrical…”
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Using a CMOS ASIC technology for the development of an integrated ISFET sensor by Dzahini, K., Gaffiot, F., Le Helley, M.

“…To take advantage of microelectronics, attempts have been made to integrate sensors in silicon and furthermore to accommodate the whole system formed of the…”
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Design automation of power integrated circuits in EDGE environment by Hebrard, L., Jacquemod, G., Boutherin, B., Le Helley, M.

“…Presents SETIPIC, a software package to forecast the electrothermal interactions in the first design steps of power integrated circuits. To give a…”
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Experimental multiprocessor architecture dedicated for solving 3D PDEs by Libs, J.-M., Siaud, B., Durupt, J., Boutherin, B., Jacquemod, G., Le Helley, M.

“…In order to achieve more accurate studies, there is a definite trend towards 3D numerical simulations, which require very long computation times. We report on…”
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High speed CMOS operational amplifier by Schwehr, S., Fuchs, T., Dzahini, K., Boutherin, B., Le Helley, M.

“…In this paper authors present a new approach to fast CMOS opamp design. This approach benefits from the advantages offered by full complementary…”
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Layout automation of CMOS analog building blocks with CADENCE by Dzahini, D., Gaffiot, F., Boutherin, B., Le Helley, M.

“…Presents a set of tools for aiding to the design of analog CMOS circuits. The procedures described can generate automatically the layout of CMOS cells. In…”
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Dedicated processor for partial differential equation solver by Theodorou, F., Gaffiot, F., Boutherin, B., Menezia, R., Le Helley, M.

“…A hardware solver for Delta Psi =f( Psi ), by the finite-difference method in 3D is presented. The general architecture is given: several identical processors…”
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SETIPIC: electrothermal simulator for power integrated circuits in EDGE environment by Hebrard, L., Klingelhofer, C., Jacquemod, G., Boutherin, B., Le Helley, M.

“…The authors present SETIPIC, a software to simulate the electrothermal interactions in the first design steps of power integrated circuits. To give a…”
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Simulation of electrothermal interactions in power integrated circuits by Hebrard, L., Jacquemod, G., Boutherin, B., Le Helley, M.

“…The authors present SETIPIC, a software package which couples electric and thermal simulations to forecast the electrothermal interactions in the first design…”
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Example of CMOS analog cells' automatic layouts: a cascode current source by Mathias, H., Hebrard, L., Jacquemod, G., Boutherin, B., Le Helley, M.

“…The authors present CLAP, a program for automatic layout generation of a cascode current source. The source is considered as a parameterized macrocell whose…”
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