Search Results - "Laraba, Asma"

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs by Renaud, Guillaume, Barragan, Manuel J., Laraba, Asma, Stratigopoulos, Haralampos-G., Mir, Salvador, Le-Gall, Hervé, Naudet, Hervé

“…This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity…”
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A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET by Poon, Chi Fung, Zhang, Wenfeng, Cho, Junho, Ma, Shaojun, Wang, Yipeng, Cao, Ying, Laraba, Asma, Ho, Eugene, Lin, Winson, Wu, Daniel Zhaoyin, Tan, Kee Hian, Upadhyaya, Parag, Frans, Yohan

“…This article describes the design of a 1.24-pJ/b 112-Gb/s PAM4 transceiver test chip in 7-nm FinFET for in-package die-to-die communication. The receiver…”
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Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique by Laraba, Asma, Stratigopoulos, Haralampos-G, Mir, Salvador, Naudet, Herve

“…Testing the static performances of high-resolution analog-to-digital converters (ADCs) consumes long test times that are disproportionately high with respect…”
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A 112-134-Gb/s PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET by de Abreu Farias Neto, Pedro Wilson, Hearne, Kay, Chlis, Ilias, Carey, Declan, Casey, Ronan, Griffin, Ben, Ngankem Ngankem, Frantz Stephane F., Hudner, James, Geary, Kevin, Erett, Marc, Laraba, Asma, Eachempatti, Haritha, Kim, Jae Wook, Zhang, Hongtao, Asuncion, Santiago, Frans, Yohan

“…This letter describes a 112-134-Gb/s PAM-4 wireline receiver (Rx) designed and fabricated in 7-nm CMOS FinFET technology. The Rx includes a T-Coil-assisted…”
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16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC by Vaz, Bruno, Lynam, Adrian, Verbruggen, Bob, Laraba, Asma, Mesadri, Conrado, Boumaalif, Ali, Mcgrath, John, Kamath, Umanath, De Le Torre, Ronnie, Manlapat, Alvin, Breathnach, Daire, Erdmann, Christophe, Farley, Brendan

“…In recent years, the need for high performance RF sampling ADCs has driven impressive developments of pipelined-SAR and pipelined ADCs, all supported by…”
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Reduced code linearity testing of pipeline adcs in the presence of noise by Laraba, A., Stratigopoulos, H., Mir, S., Naudet, H., Bret, G.

“…Reduced code testing of a pipeline analog-to-digital converter (ADC) consists of inferring the complete static transfer function by measuring the width of a…”
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A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET by Poon, Chi Fung, Zhang, Wenfeng, Cho, Junho, Ma, Shaojun, Wang, Yipeng, Cao, Ying, Laraba, Asma, Ho, Eugene, Lin, Winson, Wu, Daniel, Tan, Kee Hian, Upadhyaya, Parag, Frans, Yohan

“…This paper describes the design of a 1.24pJ/b 112Gb/s PAM4 transceiver testchip in 7nm FinFET for in-package die-to-die communication. The receiver supports…”
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A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET by Hudner, James, Carey, Declan, Casey, Ronan, Hearne, Kay, de Abreu Farias Neto, Pedro Wilson, Chlis, Ilias, Erett, Marc, Chi Fung Poon, Laraba, Asma, Hongtao Zhang, Chaitanya Ambatipudi, Sai Lalith, Mahashin, David, Upadhyaya, Parag, Frans, Yohan, Chang, Ken

“…A 112Gb/s PAM4 wireline receiver testchip is implemented in 16nm FinFET. The receiver consists of continuous-time linear equalizers, a peaking capacitance…”
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Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs by Laraba, A., Stratigopoulos, H-G, Mir, S., Naudet, H., Forel, C.

“…The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the…”
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Reduced-Code Linearity Testing of Pipeline ADCs by Laraba, Asma, Stratigopoulos, Haralampos-G, Mir, Salvador, Naudet, Herve, Bret, Gerard

“…Pipeline analog-to-digital converters have a repetitive structure, which allows analyzing their static performances by targeting only a small subset of codes…”
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