Search Results - "Laplanche, Y."

Critical dimension adapted alignment for EBDW by Weidenmueller, U., Hahmann, P., Pain, L., Jurdit, M., Henry, D., Laplanche, Y., Manakli, S., Todeschini, J.

“…Electron beam direct write (EBDW) promises a good solution in lithography applications, where standard optical lithography is not suitable. With shrinking…”
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65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications by Tavel, B., Duriez, B., Gwoziecki, R., Basso, M.T., Julien, C., Ortolland, C., Laplanche, Y., Fox, R., Sabouret, E., Detcheverry, C., Boeuf, F., Morin, P., Barge, D., Bidaud, M., Biénacel, J., Garnier, P., Cooper, K., Chapon, J.D., Trouiller, Y., Belledent, J., Broekaart, M., Gouraud, P., Denais, M., Huard, V., Rochereau, K., Difrenza, R., Planes, N., Marin, M., Boret, S., Gloria, D., Vanbergue, S., Abramowitz, P., Vishnubhotla, L., Reber, D., Stolk, P., Woo, M., Arnaud, F.

“…A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on…”
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Analyze of temporal and random variability of a 45nm SOI SRAM cell by Laplanche, Y.

“…This paper presents the analysis of a 45 nm SOI SRAM cell variability including history effects and random variability. This leads to an accurate margin…”
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65nm LP/GP mix low cost platform for multi-media wireless and consumer applications by Tavel, B., Duriez, B., Gwoziecki, R., Basso, M.T., Julien, C., Ortolland, C., Laplanche, Y., Fox, R., Saboure, E., Detcheverry, C., Boeuf, F., Morin, P., Barge, D., Bidaud, M., Bienacel, J., Garnier, P., Cooper, K., Chapon, J.D., Trouille, Y., Belledent, J., Broekaart, M., Gouraud, P., Denais, M., Huard, V., Rochereau, K., Difrenza, R., Planes, N., Marin, M., Boret, S., Gloria, D., Vanbergue, S., Abramowitz, P., Vishnubhotla, L., Reber, D., Stolk, P., Woo, M., Arnaud, F.

“…A complete 65nm CMOS platform, called LP/GP mix, has been developed employing thick oxide transistor (1.0), low power (LP) and general purpose (GP) devices on…”
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Low cost 65nm CMOS platform for Low Power & General Purpose applications by Arnaud, F., Duriez, B., Tavel, B., Pain, L., Todeschini, J., Jurdit, M., Laplanche, Y., Boeuf, F., Salvetti, F., Lenoble, D., Reynard, J.P., Wacquant, F., Morin, P., Emonet, N., Barge, D., Bidaud, M., Ceccarelli, D., Vannier, P., Loquet, Y., Leninger, H., Judong, F., Perrot, C., Guilmeau, I., Palla, R., Beverina, A., DeJonghe, V., Broekaart, M., Vachellerie, V., Bianchi, R.A., Borot, B., Devoivre, T., Bicais, N., Roy, D., Denais, M., Rochereau, K., Difrenza, R., Planes, N., Brut, H., Vishnobulta, L., Reber, D., Stolk, P., Woo, M.

“…A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional…”
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Timing verification of a 45nm SOI standard cell library by Pelloie, J, Laplanche, Y, Hawkins, C, Kundu, R

“…A reliable timing verification methodology has been developed and proven on a 45nm SOI standard cell library. This methodology is currently used at more…”
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Physical IP design for advanced SOI technologies by Laplanche, Y., Pelloie, J.-L., Frey, C., Rien, M.

“…The SOI technology is now mature for ASIC applications. Some foundries in the world are offering SOI technologies. ARM is enabling the ASIC design by…”
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65nm LP/GP mix low cost platform for multi-media wireless and consumer applications by Tavel, B., Duriez, B., Gwoziecki, R., Basso, M.T., Julien, C., Ortolland, C., Laplanche, Y., Fox, R., Sabouret, E., Detcheverry, C., Boeuf, F., Morin, P., Barge, D., Bidaud, M., Biénacel, J., Garnier, P., Cooper, K., Chapon, J.D., Trouiller, Y., Belledent, J., Broekaart, M., Gouraud, P., Denais, M., Huard, V., Rochereau, K., Difrenza, R., Planes, N., Marin, M., Boret, S., Gloria, D., Vanbergue, S., Abramowitz, P., Vishnubhotla, L., Reber, D., Stolk, P., Woo, M., Arnaud, F.

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Circuit Performance Optimization in Advanced PD-SOI CMOS Development by Chiang, W.T., Huang, Y.T., Liu, P.W., Wu, C.H., Su, C.M., Huang, Y.S., Tsai, C.H., Laplanche, Y., Pelloie, J.-L., Tsai, C.T., Ma, G.H.

“…Device optimization on partially-depleted silicon-on-insulator (PD-SOI) CMOS is systematically performed in terms of circuit switching speed and power…”
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65nm CMOS BULK to SOI comparison by Pelloie, J.L., Laplanche, Y., Chen, T.F., Huang, Y.T., Liu, P.W., Chiang, W.T., Huang, M.Y.T., Tsai, C.H., Cheng, Y.C., Tsai, C.T., Ma, G.H.

“…SOI is today mainly used for high-speed CPU applications. The advantages brought by SOI are still questioned or not clearly understood and little information…”
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Physical IP and advanced SOI design for 22nm SOI technology by Pelloie, J-L, Laabidi, S, Charafeddine, K, Laplanche, Y

“…The 22nm CMOS technology node is currently under development at the major semiconductor companies. While the process is being developed and the associated…”
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Optimal PD-SOI Technology for High Performance Applications by Chiang, W.T., Liu, P.W., Huang, Y.T., Tsai, T.L., Lin, Y.H., Tsai, C.H., Laplanche, Y., Pelloie, J.-L., Tsai, C.T., Ma, G.H.

“…We present an optimal partially-depleted silicon-on-insulator (PD-SOI) platform, which demonstrates superior performance of SOI over bulk technology. Device…”
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Gate stack optimization for 65nm CMOS Low Power and High Performance platform by DURIEZ, B, TAVEL, B, PALLA, R, BIDAUD, M, BARGE, D, DACHS, C, BRUT, H, ROY, D, MARIN, M, PAYET, F, CAGNAT, N, DIFRENZA, R, BOEUF, F, ROCHEREAU, K, DENAIS, M, STOLK, P, WOO, M, ARNAUD, F, BASSO, M. T, LAPLANCHE, Y, ORTOLLAND, C, REBER, D, WACQUANT, F, MORIN, P, LENOBLE, D

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Gate stack optimization for 65 nm CMOS low power and high performance platform by Duriez, B., Tavel, B., Boeuf, R., Basso, M.T., Laplanche, Y., Ortolland, C., Reber, D., Wacquant, R., Morin, P., Lenoble, D., Palla, R., Bidaud, M., Barge, D., Dachs, C., Brut, H., Roy, D., Marin, M., Payet, F., Cagnat, N., Difrenza, R., Rochereau, K., Denais, M., Stolk, P., Woo, M., Arnaud, F.

“…This paper demonstrates a full gate stack optimization by using post gate anneal (PGA) solution coupled with both germanium and fluorine gate predoping. We…”
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65 nm device manufacture using shaped E-Beam lithography by Pain, L., Charpin, M., Laplanche, Y., Todeschini, J., Leininger, H., Tourniol, S., Faure, R., Bossy, X., Palla, R., Beverina, A., Broekaart, M., Judong, F., Brosselin, K., Le Friec, Y., Leverd, F., De Jonghe, V., Josse, E., Hinsinger, O., Brun, P., Henry, D., Woo, M., Stolk, P., Arnaud, F.

“…In this paper, SRAM cell device manufacture using shaped electron beam lithography was developed. TEM view of SRAM cell was showed…”
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Low cost 65nm CMOS platform for low power & general purpose applications by ARNAUD, F, DURIEZ, B, REYNARD, J. P, WACQUANT, F, MORIN, P, EMONET, N, BARGE, D, BIDAUD, M, CECCARELLI, D, VANNIER, P, LOQUET, Y, LENINGER, H, TAVEL, B, JUDONG, F, PERROT, C, GUILMEAU, I, PALLA, R, BEVERINA, A, DEJONGHE, V, BROEKAART, M, VACHELLERIE, V, BIANCHI, R. A, BOROT, B, PAIN, L, DEVOIVRE, T, BICAÏS, N, ROY, D, DENAIS, M, ROCHEREAU, K, DIFRENZA, R, PLANES, N, BRUT, H, VISHNOBULTA, L, REBER, D, TODESCHINI, J, STALK, P, WOE, M, JURDIT, M, LAPLANCHE, Y, BOEUF, F, SALVETTI, F, LENOBLE, D

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A functional 0.69 /spl mu/m/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform by Arnaud, F., Boeuf, F., Salvetti, F., Lenoble, D., Wacquant, F., Regnier, C., Morin, P., Emonet, N., Denis, E., Oberlin, J.C., Ceccarelli, D., Vannier, P., Imbert, G., Sicard, A., Perrot, C., Belmont, O., Guilmeau, I., Sassoulas, P.O., Delmedico, S., Palla, R., Leverd, F., Beverina, A., DeJonghe, V., Broekaart, M., Pain, L., Todeschini, J., Charpin, M., Laplanche, Y., Neira, D., Vachellerie, V., Borot, B., Devoivre, T., Bicais, N., Hinschberger, B., Pantel, R., Revil, N., Parthasarathy, C., Planes, N., Brut, H., Farkas, J., Uginet, J., Stolk, P., Woo, M.

“…This work highlights a 65 nm CMOS technology platform for low power and general-purpose applications. A 6-T SRAM cell size of 0.69 /spl mu/m/sup 2/ with a 45…”
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