Search Results - "Lan-Chou Cho"

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network by Feng-Wei Kuo, Binsfeld Ferreira, Sandro, Huan-Neng Ron Chen, Lan-Chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Madadi, Iman, Tohidian, Massoud, Shahmohammadi, Mina, Babaie, Masoud, Bogdan Staszewski, Robert

“…We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter…”
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A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm by Babaie, Masoud, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Shahmohammadi, Mina, Staszewski, Robert Bogdan

“…We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold…”
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A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation by Xu, Kai, Kuo, Feng-Wei, Chen, Huan-Neng Ron, Cho, Lan-Chou, Jou, Chewn-Pu, Chen, Mark, Staszewski, Robert Bogdan

“…In this paper, we propose a sub-gigahertz transmitter (TX) with a physically merged digitally controlled oscillator (DCO) and digital power amplifier (DPA)…”
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An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs by Kuo, Feng-Wei, Babaie, Masoud, Chen, Huan-Neng Ron, Cho, Lan-Chou, Jou, Chewn-Pu, Chen, Mark, Staszewski, Robert Bogdan

“…We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length…”
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A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC by Chi-Yao Yu, Lu, I. S., Yen-Horng Chen, Lan-Chou Cho, Sun, C. E., Chih-Chun Tang, Hsiang-Hui Chang, Wen-Chang Lee, Sheng-Jui Huang, Tzung-Han Wu, Chinq-Shiun Chiu, Chien, G.

“…A quad-band GSM/GPRS/EDGE receiver, implemented in 65 nm CMOS, complies with the ETSI standard without the need of external SAW filters. By exploring the…”
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A 1.2-V 37-38.5-GHz eight-phase clock generator in 0.13-μm CMOS technology by CHO, Lan-Chou, LEE, Chihun, LIU, Shen-Iuan

“…A 37-38.5-GHz clock generator is presented in this paper. An eight-phase LC voltage-controlled oscillator (VCO) is presented to generate the multiphase…”
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A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology by CHO, Lan-Chou, LEE, Chihun, HUNG, Chao-Ching, LIU, Shen-Iuan

“…A 33.6-33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. To reduce the data jitter and generate the high-frequency output…”
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A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-$\mu$m CMOS by Chihun Lee, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu

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A 55nm CMOS 4-in-1 (11b/g/n, BT, FM, and GPS) radio-in-a-package with IPD front-end components directly connected to antenna by Jing-Hong Conan Zhan, Yuli Hsueh, Min Chen, Meng-Hsiung Hung, Yi-An Li, Lan-Chou Cho, Hui-Hsien Liu, Ming-Da Tsai, Ping-Yu Chen, Jui-Lin Syu, Yi-Chien Tsai, Tao-Yao Chang, Jen-Che Tsai, Sheng-Hao Chen, Ping-Hsuan Tsu, Kuo-Hao Chen, Chun-Yi Wu, Sheng Jau Wong, Chun Geik Tan, Chien, George

“…This paper presents a 55nm 4-in-1 (11b/g/n, BT, FM, and GPS) radio assembled side-by-side with a 3-metal layer integrated-passive-device (IPD) chip in a QFN40…”
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Cascaded Multi-Stage Directional Coupler on Silicon-on-Insulator by Tang, Cheng-Tse, Jou, Chewn-Pu, Cho, Lan-Chou, Kuo, Fong-Wei, Chung, Ming-Yang, Huang, Tai-Chun, Hung, Yung-Jr

“…We demonstrate the feasibility of a width-engineered cascaded multi-stage directional coupler on silicon-on-insulator for broadband (within 5% power variation…”
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A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic by Kuo, Feng-Wei, Zong, Zhirui, Chen, Huan-Neng Ron, Cho, Lan-Chou, Jou, Chewn-Pu, Chen, Mark, Staszewski, Robert Bogdan

“…This paper presents a digitally controlled frequency generator for dual frequency-band radar system that is optimized for 16 nm FinFET CMOS. It is based on a…”
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A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology by Chihun Lee, Lan-Chou Cho, Shen-Iuan Liu

“…A CMOS 44GHz divide-by-4/5 dual-modulus prescaler is presented. The scaled inductive peaking technique and the merged NOR-FF circuits are used to achieve the…”
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Towards Ultra-Low-Voltage and Ultra-Low-Power Discrete-Time Receivers for Internet-of-Things by Kuo, Feng-Wei, Ferreira, Sandro Binsfeld, Chen, Ron, Cho, Lan-Chou, Jou, Chewn-Pu, Chen, Mark, Babaie, Masoud, Staszewski, Robert Bogdan

“…In this paper, we investigate an impact of voltage supply scaling on power consumption and performance of a new class of wireless receivers (RX) for…”
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3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology by Tsai, Kun-Hung, Cho, Lan-Chou, Wu, Jia-Hao, Liu, Shen-Iuan

“…The frequency divider (FD) is one of the key components in very-high-frequency (VHF) PLLs. Conventionally, injection-locked frequency divider (ILFD) , Miller…”
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A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC by Lu, I S.-C, Chi-yao Yu, Yen-horng Chen, Lan-chou Cho, Sun, Chih-hao Eric, Chih-Chun Tang, Chien, G

“…Over the last decade, significant progress has been made towards increasing integration and reducing bill of material (BOM) for GSM/GPRS/EDGE cellular systems…”
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A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- \mum CMOS by Lee, Chihun, Cho, Lan-Chou, Wu, Jia-Hao, Liu, Shen-Iuan

“…A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The…”
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A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS by Cho, Lan-Chou, Lee, Chihun, Liu, Shen-Iuan

“…A 33.6-to-33.8 Gb/s burst-mode CDR circuit is realized in 90nm CMOS technology. The LC gated VCO, the phase selector the input matching circuit, and the…”
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A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS by Feng-Wei Kuo, Pourmousavian, Seyednaser, Siriburanon, Teerachot, Ron Chen, Lan-chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Staszewski, Robert Bogdan

“…This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a…”
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A 0.85mm 2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD 2 Self-Suppression and Pulling Mitigation by Xu, Kai, Kuo, Feng-Wei, Chen, Huan-Neng Ron, Cho, Lan-Chou, Jou, Chewn-Pu, Chen, Mark, Staszewski, Robert Bogdan

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A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter by Feng-Wei Kuo, Binsfeld Ferreira, Sandro, Babaie, Masoud, Chen, Ron, Lan-chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Guanzhong Huang, Madadi, Iman, Tohidian, Massoud, Staszewski, Robert Bogdan

“…We present a new ultra-low-power (ULP) transceiver for Internet-of-Things (IoT) optimized for 28-nm CMOS. The receiver (RX) employs a high-rate (up to 10 GS/s)…”
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