Search Results - "Lahri, R."

Gate oxide charge-to-breakdown correlation to MOSFET hot-electron degradation by Davis, M., Lahri, R.

“…Substrate current by itself is found not to be a sufficient indicator of degradation. Experiments using active-area test capacitors with and without poly edges…”
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Potential distributions in metal-Semiconductor and p-i-n structures on a-Si:H by capacitive techniques by Lahri, R., Min-Koo Han, Anderson, W.A.

“…C(0),f and C-V-f characteristics have been used to find the barrier profile and depletion width in several Schottky (i-n + ) structures on a-Si: H. Depletion…”
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Image force effects on carrier collection in a -Si:H solar cells by Han, Min-Koo, Anderson, Wayne A., Lahri, R., Coleman, John

“…A modified carrier collection model of a-Si:H Schottky-barrier solar cells is proposed to explain the falloff of short wavelength carrier collection…”
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Effects of the undoped layer on characteristics of amorphous silicon Schottky diodes by Han, M.-K., Anderson, W.A., Onuma, Y., Sung, P., Lahri, R., Coleman, J.

“…The effects of undoped layer thickness on the dark and illuminated I-V characteristics of hydrogenated amorphous silicon Schottky barrier solar cells are…”
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Improving hot-electron reliability through circuit analysis and design by Wang, H., De, H., Lahri, R., Haueisen, D.

“…On-chip hot-electron test/stress structures have been developed. These structures provide insight into device degradation under real circuit operation. This…”
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Submicron Large-Angle-Tilt Implanted Drain technology for mixed-signal applications by Hung-Sheng Chen, Ji Zhao, Chih Sieh Teng, Moberly, L., Lahri, R.

“…This paper reports the use of LATID in submicron MOS technology to improve both analog and digital device performance and reliability. It is demonstrated that…”
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Mismatch drift: a reliability issue for analog MOS circuits by Michael, C., Wang, H., Teng, C.S., Shibley, J., Lewicki, L., Shyu, C.-M., Lahri, R.

“…Mismatch drift is a major process reliability issue for analog and mixed-signal designs. Mismatch stability was examined for a 0.8- mu m CMOS process using a…”
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Development of design rules for reliable tungsten plugs using simulations by IslamRaja, M.M., Bariya, A.J., Saraswat, K.C., Cappelli, M.A., McVittie, J.P., Moberly, L., Lahri, R.

“…Design rules for the fabrication of reliable tungsten via plugs, produced using blanket tungsten deposition and etch-back, have been developed using…”
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Ion beam shadowing effect in submicromometer large-angle-tilt implanted drain (latid) MOSFETs by HUNG-SHENG CHEN, CHIH-SIEH TENG, MOBERLY, L, LAHRI, R

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Ion beam shadowing effect in submicrometer large-angle-tilt implanted drain (LATID) MOSFETs by Hung-Sheng Chen, Chih-Sieh Teng, Moberly, Larry, Lahri, Rajeeva

“…An orientation-dependent device characteristic in LATID MOSFETs is reported. By controlled device fabrication splits, it is confirmed that the…”
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Analog characteristics of drain engineered submicron MOSFETs for mixed-signal applications by Chen, Hung-Sheng, Teng, Chih Sieh, Zhao, Ji, Moberly, Larry, Lahri, Rajeeva

“…Drain engineered MOSFETs are compared in terms of their impact on analog performance for submicron mixed-signal applications. The high energy implanted lightly…”
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Poly emitter bipolar hot carrier effects in an advanced BiCMOS technology by Joshi, S.P., Lahri, R., Lage, C.

“…Hot carrier effects due to reverse biasing of emitter-base junction in a poly emitter bipolar transistor are discussed. Degradation of transistor current gain…”
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Characterization of transistor mismatch for statistical CAD of submicron CMOS analog circuits by Abel, C.J., Michael, C., Ismail, M., Teng, C.S., Lahri, R.

“…The use of a four-parameter MOS model to characterize drain current mismatch is discussed. Guidelines for the accurate and repeatable measurement of transistor…”
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Characterization and optimization of amorphous silicon solar cells by variation of device geometry by Min-Koo Han, Anderson, W.A., Lahri, R., Wiesmann, H.

“…Characteristics of N-I-P hydrogenated amorphous silicon solar cells have been studied systematically by varying the thickness of each layer. Open circuit…”
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0.6 μm, single poly advanced BiCMOS (ABiC IV) technology for ASIC applications by Iranmanesh, A., Ilderem, V., Solheim, A., Blair, C., Lam, L., Haas, F., Leibiger, S., Bouknight, L., Lahri, R., Biswal, M., Bastani, B.

“…An advanced BiCMOS technology (ABiC IV), developed by integration of high-performance CMOS devices with a state of the art bipolar process, is presented. The…”
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Transient substrate current effects on n-channel MOSFET device lifetime by Wang, H., Davis, M., Lahri, R.

“…The n-channel MOSFET transient substrate current during dynamic hot-carrier stressing has been found to be a strong function of the rise and fall time of the…”
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A 2.5 ns ECL 1616 multiplier by Roberts, S., Snyder, W., Chin, H., Hingarh, H., Leibiger, S., Lahri, R., Bouknight, L., Biswal, M.

“…A 16*16 b integer multiplier is described that has achieved a measured delay of less than 2.5 ns, register to register, for a full 16*16 multiply. It was…”
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An optimized gate oxide breakdown test by activating oxide traps at low fields by Wang, Michael, Geha, Guo, Messick, Lahri

“…In this paper, an optimized current ramp charge to breakdown test is evaluated. This methodology is more sensitive to oxide defects than the JEDEC recommended…”
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Poly emitter bipolar transistor optimization for an advanced BiCMOS technology by Landau, B., Bastani, B., Haueisen, D., Lahri, R., Joshi, S., Small, J.

“…Two approaches involving phosphorus- and arsenic-doped poly emitters for bipolar device optimization in a 1 mu m BiCMOS process are reported. An evaluation…”
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Submicron BiCMOS technologies for supercomputer and high speed system implementation by Bastani, B., Biswal, M., Iranmanesh, A., Lage, C., Bouknight, L., Ilderem, V., Solheim, A., Burger, W., Lahri, R., Small, J.

“…Submicron process technologies that allow a full implementation of CPU, first-level cache, second-level cache, and the main memory in the BiCMOS approach are…”
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