Search Results - "Lagrain, P."

Enabling focused ion beam sample preparation for application in reverse tip sample scanning probe microscopy by Lagrain, P., Paulussen, K., Grieten, E., Van den Bosch, G., Rachidi, S., Yudistira, D., Wouters, L., Hantschel, T.

“…Focused ion beam (FIB) has become a powerful tool for transmission electron microscopy sample preparation in the nanoelectronics industry and has in recent…”
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Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS by Veloso, A., Hellings, G., Cho, M. J., Simoen, E., Devriendt, K., Paraschiv, V., Vecchio, E., Tao, Z., Versluijs, J. J., Souriau, L., Dekkers, H., Brus, S., Geypen, J., Lagrain, P., Bender, H., Eneman, G., Matagne, P., De Keersgieter, A., Fang, W., Collaert, N., Thean, A.

“…We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW)…”
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Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells by Veloso, A., Parvais, B., Matagne, P., Simoen, E., Huynh-Bao, T., Paraschiv, V., Vecchio, E., Devriendt, K., Rosseel, E., Ercken, M., Chan, B. T., Delvaux, C., Altamirano-Sanchez, E., Versluijs, J. J., Tao, Z., Suhard, S., Brus, S., Sibaja-Hernandez, A., Waldron, N., Lagrain, P., Richard, O., Bender, H., Chasin, A., Kaczer, B., Ivanov, T., Ramesh, S., De Meyer, K., Ryckaert, J., Collaert, N., Thean, A.

“…We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same…”
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Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration by Mertens, H., Ritzenthaler, R., Pena, V., Santoro, G., Kenis, K., Schulze, A., Litta, E. D., Chew, S. A., Devriendt, K., Chiarella, R., Demuynck, S., Yakimets, D., Jang, D., Spessot, A., Eneman, G., Dangol, A., Lagrain, P., Bender, H., Sun, S., Korolik, M., Kioussis, D., Kim, M., Bu, Chen, S. C., Cogorno, M., Devrajan, J., Machillot, J., Yoshida, N., Kim, N., Barla, K., Mocuta, D., Horiguchi, N.

“…We report on CMOS-integrated vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs with in-situ doped source-drain stressors and dual work function…”
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Record performance Top-down In0.53Ga0.47As vertical nanowire FETs and vertical nanosheets by Ramesh, S., Ivanov, Ts, Putcha, V., Alian, A., Sibaja-Hernandez, A., Rooyackers, R., Camerotto, E., Milenin, A., Pinna, N., El Kazzi, S., Veloso, A., Lin, D., Lagrain, P., Favia, P., Collaert, N., De Meyer, K.

“…We report high performance, dry etched In 0.53 Ga 0.47 As vertical nanowire and vertical nanosheet devices, fabricated using a VLSI compatible process flow…”
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First demonstration of 15nm-WFIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain by Mitard, J., Witters, L., Arimura, H., Sasaki, Y., Milenin, A. P., Loo, R., Hikavyy, A., Eneman, G., Lagrain, P., Mertens, H., Sioncke, S., Vrancken, C., Bender, H., Barla, K., Horiguchi, N., Mocuta, A., Collaert, N., Thean, A. V.-Y

“…This work demonstrates the feasibility of an inversion-mode relaxed Ge n-FinFET scaled down to 15-nm fin width and sub-40-nm gate length. CMOS-compatible…”
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