Search Results - "Laegu Kang"

Electrical and reliability characteristics of ZrO2 deposited directly on Si for gate dielectric application by Qi, Wen-Jie, Nieh, Renee, Lee, Byoung Hun, Kang, Laegu, Jeon, Yongjoo, Lee, Jack C.

“…ZrO 2 thin film has been studied as an alternative gate dielectric. It was deposited directly on a Si substrate by reactive sputtering. An equivalent oxide…”
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Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric by Laegu Kang, Byoung Hun Lee, Wen-Jie Qi, Yongjoo Jeon, Nieh, R., Gopalan, S., Onishi, K., Lee, J.C.

“…Electrical and reliability properties of ultrathin HfO/sub 2/ have been investigated. Pt electroded MOS capacitors with HfO/sub 2/ gate dielectric (physical…”
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Dual Silicide SOI CMOS Integration with Low-Resistance PtSi PMOS Contacts by Zollner, S., Grudowski, P., Thean, A., Jawarani, D., Karve, G., White, T., Bolton, S., Desjardins, H., Chowdhury, M., Kyuhwan Chang, Jahanbani, M., Noble, R., Lovejoy, L., Rossow, M., Denning, D., Goedeke, D., Filipiak, S., Garcia, R., Raymond, M., Dhandapani, V., Da Zhang, Laegu Kang, Crabtree, P., Zhu, X., Kottke, M.L., Gregory, R., Fejes, P., Wang, X.-D., Theodore, D., Taylor, W.J., Bich-Yen Nguyen

“…We demonstrate a dual silicide integration on a SOI CMOS platform with robust low-resistance PtSi PMOS contacts. Compared to NiSi, the specific contact…”
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Thermal stability and electrical characteristics of ultrathin hafnium oxide gate dielectric reoxidized with rapid thermal annealing by Lee, Byoung Hun, Kang, Laegu, Nieh, Renee, Qi, Wen-Jie, Lee, Jack C.

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Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application by Byoung Hun Lee, Laegu Kang, Wen-Jie Qi, Renee Nieh, Yongjoo Jeon, Katsunori Onishi, Lee, J.C.

“…Physical, electrical and reliability characteristics of ultra thin HfO/sub 2/ as an alternative gate dielectric were studied for the first time. Crucial…”
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Ultrathin zirconium silicate film with good thermal stability for alternative gate dielectric application by Qi, Wen-Jie, Nieh, Renee, Dharmarajan, Easwar, Lee, Byoung Hun, Jeon, Yongjoo, Kang, Laegu, Onishi, Katsunori, Lee, Jack C.

“…Zirconium silicate (ZrSixOy) films have been sputtered by comagnetron-reactive sputtering. The composition of ZrSixOy has been controlled by adjusting the…”
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Avoiding plasma induced damage to gate oxide with conductive top film (CTF) on PECVD contact etch stop layer by Seung-Chul Song, Filipiak, S., Perera, A., Turner, M., Huang, F., Anderson, S.G.H., Laegu Kang, Byoung Min, Menke, D., Tukunang, S., Venkatesan, S.

“…Significantly reduced plasma damage is demonstrated by including a thin conductive top film (CTF) on the contact etch stop layer (ESL) for the first time,…”
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Effects of Hf contamination on the properties of silicon oxide metal–oxide–semiconductor devices by Kang, Chang Seok, Onishi, Katsunori, Kang, Laegu, Lee, Jack C.

“…Effects of hafnium (Hf) contamination on the properties of n+-polycrystalline-Si/SiO2/Si metal–oxide–semiconductor (MOS) devices were investigated using p-type…”
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High Performance NMOS Transistors for 45nm SOI Technologies by Bo, Xiang-Zheng, Kang, Laegu, Luo, T., Junker, K., Zollner, S., Spencer, G., Kolagunta, V., Cheek, J.

“…We demonstrate NMOS performance enhancements of up to ~18% for applications in a 45 nm SOI technology. The performance boost was achieved using high…”
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Study of hafnium dioxide as a future gate dielectric and implementation of polysilicon electrodes for hafnium dioxide films by Kang, Laegu

“…Silicon Dioxide (SiO2) has been used as the primary gate dielectric material in field-effect devices due to good interface, low gate leakage currents, and…”
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Effects of SOI film thickness on high-performance microprocessor by 0.13 /spl mu/m Partially-Depleted SOI CMOS technology by Jianan Yang, Byoung Min, Yasuhito, Laegu Kang, Walker, Mendicino, Yeap, Foisy, Cox, Cartwright, Venkatesan

“…This paper describes how SOI film thickness affects performance and power consumption of a Partially-Depleted (PD) SOI microprocessor. System level speed/power…”
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High performance partially depleted SOI using spike RTA by Kang, Grudowski, Veer Dhandapani, Yongjoo Jeon, Goktepeli, Byoung Min, Yeap, Foisy, Anderson, Mendicino, Venkatesan

“…Thinner Si body (700 /spl Aring/) SOI CMOS was successfully demonstrated with spike RTA on 0.13 /spl mu/m technology with 45 nm gate lengths and 16/spl Aring/…”
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Temperature effect on the reliability of ZrO/sub 2/ gate dielectric deposited directly on silicon by Wen-Jie Qi, Nieh, R., Onishi, R., Byoung Hun Lee, Laegu Kang, Yongjoo Jeon, Gopalan, S., Lee, J.C.

“…Temperature effect on the reliability of ZrO/sub 2/ gate dielectric has been presented. High effective voltage-ramp breakdown field was observed. The…”
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Performance of MOSFETs with ultra thin ZrO/sub 2/ and Zr silicate gate dielectrics by Wen-Jie Qi, Nieh, R., Byoung Hun Lee, Onishi, K., Laegu Kang, Yongjoo Jeon, Lee, J.C., Kaushik, V., Bich-Yen Neuyen, Prabhu, L., Eisenbeiser, K., Finder, J.

“…In this paper, we report the transistor performance of both PMOS and NMOS fabricated with ZrO/sub 2/ and Zr-silicate gate dielectrics. These high-k films…”
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MOSCAP and MOSFET characteristics using ZrO/sub 2/ gate dielectric deposited directly on Si by Wen-Jie Qi, Renee Nieh, Byoung Hun Lee, Laegu Kang, Yongjoo Jeon, Onishi, K., Ngai, T., Banerjee, S., Lee, J.C.

“…MOSCAP and MOSFET characteristics using ZrO/sub 2/ gate dielectric deposited directly on Si have been investigated. Thin equivalent oxide thickness (EOT), low…”
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