Search Results - "La Rue, G.S."

A 12-Bit Nonlinear DAC for Direct Digital Frequency Synthesis by Zhihe Zhou, La Rue, G.S.

“…A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-mum SOI CMOS process. The nonlinear DAC can implement a piecewise-linear…”
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A Novel SiGe PIN Diode SPST Switch for Broadband T/R Module by Pinping Sun, Upadhyaya, P., Dong-Ho Jeong, Heo, D., La Rue, G.S.

“…A novel octagonal SiGe p-type intrinsic n-type (PIN) diode single pole single throw (SPST) switch is first implemented in a standard 0.18-mum SiGe BiCMOS…”
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Fast acquisition clock and data recovery circuit with low jitter by Ruiyuan Zhang, La Rue, G.S.

“…This paper presents a half-rate clock and data recovery circuit (CDR)that combines the fast acquisition of a phase selection (PS) delay-locked loop (DLL) with…”
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Accurate SPICE models for CMOS analog radiation-hardness-by-design by Champion, C.L., La Rue, G.S.

“…A new accurate modeling technique based on conformal mapping provides SPICE models for edgeless field-effect transistors (FETs) with arbitrary gate geometries…”
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Gigabit complementary HFET communication circuits: 16:1 multiplexer, 1:16 demultiplexer and 16/spl times/16 crosspoint switch by La Rue, G.S., Dao, T.A.

“…Three high-speed, low-power integrated circuits are intended for data communication applications in space. A 16:1 multiplexer (1.8 Gb/s, 53 mW), 1:16…”
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A 5 GHz Digitally Controlled Synthesizer in 90 nm CMOS by Hamon, B.J., Mandhanya, S., La Rue, G.S.

“…A digitally controlled synthesizer (DCS) using a delay accumulator and a frequency divider is presented. The system operates with an output tuning range of…”
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40 Gbps SiGe pattern generator IC with variable clock skew and output levels by Zahller, M.J., La Rue, G.S.

“…A single-chip 40 Gbps pattern generator design in 0.18 mum SiGe BiCMOS technology is described. An on-chip 128times128 bit RAM with an access time of 3 ns…”
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Parallel phase accumulator architecture for DDFS by Horowitz, I., La Rue, G.S.

“…A parallel architecture is described for a phase accumulator (PA) in a direct digital frequency synthesizer (DDFS) intended for space-based applications. A…”
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Clock and data recovery circuits with fast acquisition and low jitter by Ruiyuan Zhang, La Rue, G.S.

“…This paper presents a half-rate clock and data recovery circuit (CDR) that combines the best features, fast acquisition and low jitter, of digital phase…”
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Clock and data recovery circuits with fast acquisition and low jitter by Ruiyuan Zhang, La Rue, G.S.

“…This paper presents a half-rate clock and data recovery circuit (CDR) that combines the best features, fast acquisition and low jitter, of digital phase…”
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Design of a radiation-hard DDFS by Zhihe Zhou, Horowitz, I., La Rue, G.S.

“…A radiation hardened direct digital frequency synthesizer (DDFS) was designed in 0.18 mum CMOS technology. A novel 14-bit nonlinear DAC is used to generate…”
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Non-linear DAC implementations in DDFS by Zhihe Zhou, Horowitz, I., La Rue, G.S.

“…A technique to reduce ROM size and therefore power dissipation in direct digital frequency synthesizers (DDFS) is to use a non-linear DAC to approximate the…”
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A low-power 16-bit 500 kS/s ADC by Haidong Guo, Rector, D.M., la Rue, G.S.

“…A 6.2 mW 16-bit 500 kSps charge redistribution self calibrating successive approximation analog-to-digital converter (ADC) is described. It has an input range…”
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A low-power low-noise sensor IC by Haidong Guo, Champion, C.L., Rector, D.M., La Rue, G.S.

“…An IC for acquisition of 16 electrophysiology signals in mice is described. Each channel includes programmable gains from 10 to 1000, a 7 kHz low-pass…”
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