Search Results - "Kwak, K.H"
-
1
Effects of Allopurinol and Apocynin on Renal Ischemia-Reperfusion Injury in Rats
Published in Transplantation proceedings (01-07-2015)“…Abstract Background This study evaluated the effects of allopurinol (ALP), a xanthine oxidase inhibitor, and apocynin (APC), a NADPH oxidase inhibitor,…”
Get full text
Journal Article -
2
-
3
-
4
A 500-MHz DDR High-Performance 72-Mb 3-D SRAM Fabricated With Laser-Induced Epitaxial c-Si Growth Technology for a Stand-Alone and Embedded Memory Application
Published in IEEE transactions on electron devices (01-02-2010)“…For the first time, the smallest 3-D stacked six-transistor (6T) static-random-access-memory (SRAM) cell technology is successfully developed by using a laser…”
Get full text
Journal Article -
5
Identification of an intermediate state as spermatogonial stem cells reprogram to multipotent cells
Published in Molecules and cells (01-05-2010)“…The aim of this study was to understand the mechanisms that allow mSSC lines to be established from SSCs. Small, multilayer clumps of SSCs formed during two to…”
Get more information
Journal Article -
6
Development of viscous PR flow technology for 0.26 /spl mu/m contact pitch on 0.84 /spl mu/m/sup 2/ SRAM cell [photoresist flow]
Published in ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003 (2003)“…The PR (photoresist) flow process for small contact patterning is difficult to predict and optimize because it is sensitively affected by the process…”
Get full text
Conference Proceeding -
7
Ultra-low power and high speed SRAM for mobile applications using single Poly-Si gate 90 nm CMOS technology
Published in 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) (2003)“…High speed and ultra-low power SRAM using single gate CMOS technology was developed. The drive currents of NMOSFET and PMOSFET were 410 /spl mu/A//spl mu/m and…”
Get full text
Conference Proceeding -
8
Highly manufacturable 100 nm 6T low power SRAM with single poly-Si gate technology
Published in 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672) (2003)“…As scaling down the device, it is difficult to control the standby leakage and device performance at the same time. In this work, 6-transistor SRAM cell using…”
Get full text
Conference Proceeding -
9
Novel 3-dimensional 46F/sup 2/ SRAM technology with 0.294um/sup 2/ S/sup 3/ (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)
Published in Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) (2004)“…We have realized a 46F/sup 2/ SRAM cell size of 0.294 /spl mu/m/sup 2/ with 80 nm technology and single stack S/sup 3/ cell technology. SSTFTs and vertical…”
Get full text
Conference Proceeding -
10
Highly manufacturable 32 Mb ULP-SRAM technology by using dual gate process for 1.5 V Vcc operation
Published in 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) (2002)“…For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated…”
Get full text
Conference Proceeding -
11
Fabrication and characteristics of novel load PMOS SSTFT (Stacked Single-crystal Thin Film Transistor) for 3-Dimensional SRAM memory cell
Published in 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573) (2004)“…The PMOS SSTFT (stacked single-crystal thin film transistor) is developed for achieving the smallest SRAM cell size, such as 45F/sup 2/, and low power mobile…”
Get full text
Conference Proceeding