A 2.6-GByte/s multipurpose chip-to-chip interface

A 2.6 GByte/s megacell that interfaces to single or double byte wide DRAMs or logic chips is implemented using 0.35-0.18 /spl mu/m CMOS technologies. Special I/O circuits are used to guarantee 800 Mbit/s/pin data rate. Microwave PC board design methodologies are used to achieve the maximum possible...

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Bibliographic Details

Published in:	IEEE journal of solid-state circuits Vol. 33; no. 11; pp. 1617 - 1626
Main Authors:	Lau, B., Yiu-Fai Chan, Moncayo, A., Ho, J., Allen, M., Salmon, J., Liu, J., Muthal, M., Lee, C., Nguyen, T., Horine, B., Leddige, M., Kuojim Huang, Wei, J., Leung Yu, Tarver, R., Yuwen Hsia, Vu, R., Tsern, F., Haw-Jyh Liaw, Hudson, J., Nguyen, D., Donnelly, K., Crisp, R.
Format:	Journal Article
Language:	English
Published:	IEEE 01-11-1998
Subjects:	Application specific integrated circuits Bandwidth Circuit testing Clocks CMOS logic circuits CMOS technology Delay Microwave theory and techniques Random access memory Voltage
Online Access:	Get full text
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