Search Results - "Kuo-Hsing Kao"

Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs by Kuo-Hsing Kao, Verhulst, A. S., Vandenberghe, W. G., Soree, B., Groeseneken, G., De Meyer, K.

“…Germanium is a widely used material for tunnel FETs because of its small band gap and compatibility with silicon. Typically, only the indirect band gap of Ge…”
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Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters by Sung, Po-Jung, Chang, Shu-Wei, Kao, Kuo-Hsing, Wu, Chien-Ting, Su, Chun-Jung, Cho, Ta-Chun, Hsueh, Fu-Kuo, Lee, Wen-Hsi, Lee, Yao-Jen, Chao, Tien-Sheng

“…In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were…”
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A Dopingless FET With Metal-Insulator-Semiconductor Contacts by Kao, Kuo-Hsing, Chen, Liang-Yu

“…By adopting the charge-plasma concept, dopingless FETs with metal-semiconductor and metal-insulator-semiconductor (MIS) contacts in parallel at the…”
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Subthreshold Swing Saturation of Nanoscale MOSFETs Due to Source-to-Drain Tunneling at Cryogenic Temperatures by Kao, Kuo-Hsing, Wu, Tzung Rang, Chen, Hong-Lin, Lee, Wen-Jay, Chen, Nan-Yow, Ma, William Cheng-Yu, Su, Chun-Jung, Lee, Yao-Jen

“…According to quantum transport simulations, source-to-drain tunneling (SDT) has been recognized as the main cause leading to subthreshold swing (SS) saturation…”
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Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets by Kuo-Hsing Kao, Verhulst, A. S., Vandenberghe, W. G., Soree, B., Magnus, W., Leonelli, D., Groeseneken, G., De Meyer, K.

“…We investigate a promising tunnel FET configuration having a gate on the source only, which is simultaneously exhibiting a steeper subthreshold slope and a…”
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Device simulations with A U-Net model predicting physical quantities in two-dimensional landscapes by Lee, Wen-Jay, Hsieh, Wu-Tsung, Fang, Bin-Horn, Kao, Kuo-Hsing, Chen, Nan-Yow

“…Although Technology Computer-Aided Design (TCAD) simulation has paved a successful and efficient way to significantly reduce the cost of experiments under the…”
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Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs by Kumar, Malkundi Puttaveerappa Vijay, Chia-Ying Hu, Kuo-Hsing Kao, Yao-Jen Lee, Tien-Sheng Chao

“…This paper presents the impacts of an advanced shell doping profile (SDP) on the electrical characteristics of a junctionless (JL) FET in terms of OFF-current,…”
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Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors by Verreck, D., Verhulst, A. S., Kuo-Hsing Kao, Vandenberghe, W. G., De Meyer, K., Groeseneken, G.

“…The tunnel field-effect transistor (TFET) is a promising candidate to replace the metal-oxide-semiconductor field-effect transistor in advanced technology…”
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First Demonstration of Ferroelectric Tunnel Thin-Film Transistor Nonvolatile Memory With Polycrystalline-Silicon Channel and HfZrO } Gate Dielectric by Ma, William Cheng-Yu, Su, Chun-Jung, Kao, Kuo-Hsing, Lee, Yao-Jen, Lin, Ju-Heng, Wu, Pin-Hua, Chang, Jui-Che, Yen, Cheng-Lun, Tseng, Hsin-Chun, Liao, Hsu-Tang, Chou, Yu-Wen, Chiu, Min-Yu, Chen, Yan-Qing

“…In this work, the nonvolatile memory constructed on the tunnel thin-film transistors (tunnel-TFTs) using polycrystalline-silicon channel featuring…”
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Impact of Nanosheet Thickness on Performance and Reliability of Polycrystalline-Silicon Thin-Film Transistors With Double-Gate Operation by Ma, William Cheng-Yu, Su, Chun-Jung, Kao, Kuo-Hsing, Guo, Jing-Qiang, Wu, Cheng-Jun, Wu, Po-Ying, Hung, Jia-Yuan

“…In this work, the polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with double gates and nanosheet (NSH) channel structures were fabricated to…”
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Inherent Dipole Layer Formation Driven by Surface Energy at Nonplanar Dielectric Interface by Fang, Yu, Lee, Wen-Jay, Yang, An-Chen, Chen, Guan-Peng, Chen, Nan-Yow, Kao, Kuo-Hsing

“…This work investigates the correlation between dipole formation and surface energy at a nonplanar dielectric interface on a Si nanowire (NW) by means of…”
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Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation by Kumar, Kunal, Hsieh, Yu-Feng, Liao, Jen-Hong, Kao, Kuo-Hsing, Wang, Yeong-Her

“…It is well known that there is a critical Sn content for a GeSn alloy, at which the conduction band edges at <inline-formula> <tex-math notation="LaTeX">{L}…”
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Counterdoped Pocket Thickness Optimization of Gate-on-Source-Only Tunnel FETs by Kuo-Hsing Kao, Verhulst, A. S., Vandenberghe, W. G., De Meyer, K.

“…The optimized tunnel field-effect transistor with a gate electrode overlapping the source region exhibits a steeper subthreshold swing (SS) and a higher…”
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Undoped and Doped Junctionless FETs: Source/Drain Contacts and Immunity to Random Dopant Fluctuation by Chen, Liang-Yu, Hsieh, Yu-Feng, Kao, Kuo-Hsing

“…By using numerical simulations, we demonstrate that a proper source/drain contacting strategy not only boosts the on-currents, but also eliminates random…”
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Insight into Latchup Risk in 28nm Planar Bulk Technology for Quantum Computing Applications by Serbulova, Kateryna, Qiu, Zi-En, Chen, Shih-Hung, Grill, Alexander, Kao, Kuo-Hsing, De Boeck, Jo, Groeseneken, Guido

“…In this work, impact of cryogenic operation temperatures on latchup in 28nm planar bulk CMOS technology is discussed for quantum computing applications…”
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Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs by Chen, Si-Hua, Lian, Shang-Wei, Wu, Tzung Rang, Chang, Tay-Rong, Liou, Jia-Ming, Lu, Darsen D., Kao, Kuo-Hsing, Chen, Nan-Yow, Lee, Wen-Jay, Tsai, Jyun-Hwei

“…The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically…”
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Improving the Electrical Performance of a Quantum Well FET With a Shell Doping Profile by Heterojunction Optimization by Kumar, Malkundi Puttaveerappa Vijay, Chia-Ying Hu, Walke, Amey Mahadev, Kuo-Hsing Kao, Tien-Sheng Chao

“…This paper investigates the impacts of typical semiconductor material properties-electron affinity, bandgap, and dielectric constant, on the electrical…”
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Modeling the impact of junction angles in tunnel field-effect transistors by Kao, Kuo-Hsing, Verhulst, Anne S., Vandenberghe, William G., Sorée, Bart, Groeseneken, Guido, Meyer, Kristin De

“…► Modeling the dominant tunnel path length of tunnel-FETs for various junction angles. ► Large tunnel areas predominate the improvement for junction angles…”
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Reliability Mechanisms of LTPS-TFT With [Formula Omitted] Gate Dielectric: PBTI, NBTI, and Hot-Carrier Stress by Ma, Ming-Wen, Chen, Chih-Yang, Wu, Woei-Cherng, Su, Chun-Jung, Kao, Kuo-Hsing, Chao, Tien-Sheng, Lei, Tan-Fu

“…In this paper, a comprehensive study of the reliability mechanisms of high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with…”
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Characteristics of PBTI and Hot Carrier Stress for LTPS-TFT With High- \kappa Gate Dielectric by MA, Ming-Wen, CHEN, Chih-Yang, SU, Chun-Jung, WU, Woei-Chemg, WU, Yi-Hong, KAO, Kuo-Hsing, CHAO, Tien-Sheng, LEI, Tan-Fu

“…In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film…”
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