Search Results - "Kuchcinski, K"

Time-energy design space exploration for multi-layer memory architectures by Szymanek, R., Catthoor, F., Kuchcinski, K.

“…This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized…”
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Automated transformation of algorithms into register-transfer level implementations by Zebo Peng, Kuchcinski, K.

“…This paper describes a high-level synthesis system, called CAMAD, for transforming algorithms into hardware implementation structures at register-transfer…”
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Scheduling of conditional process graphs for the synthesis of embedded systems by Eles, P., Kuchcinski, K., Peng, Z., Doboli, A., Pop, P.

“…We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target…”
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Partial task assignment of task graphs under heterogeneous resource constraints by Szymanek, Radoslaw, Krzysztof, Krzysztof

“…This paper presents a novel partial assignment technique (PAT) that decides which tasks should be assigned to the same resource without explicitly defining…”
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Implementation aspects of a novel speech packet loss concealment method by Svensson, H., Owall, V., Kuchcinski, K.

“…A speech data packet loss concealment algorithm based on pitch period repetition is presented and a novel low complexity method to refine a pitch period…”
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An approach to high-level synthesis using constraint logic programming by Kuchcinski, K.

“…Presents a new method for modeling and solving high-level synthesis problems. In our approach, finite-domain constraints and the related constraint-solving…”
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Integrated resource assignment and scheduling of task graphs using finite domain constraints by Kuchcinski, K.

“…This paper presents an approach to modeling of task graphs using finite domain constraints. The synthesis of such models into an architecture consisting of…”
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Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture by Raffin, E, Wolinski, C, Charot, F, Kuchcinski, K, Guyetant, S, Chevobbe, S, Casseau, E

“…This paper presents a system for application scheduling, binding and routing for a run-time reconfigurable operator based multimedia architecture (ROMA). We…”
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Task assignment and scheduling under memory constraints by Szymanek, R., Kuchcinski, K.

“…Many DSP and image processing embedded systems have hard memory constraints which makes it difficult to find a good task assignment and scheduling which…”
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Performance oriented partitioning for time-multiplexed FPGA's by Andersson, P., Kuchcinski, K.

“…Time-multiplexing is a promising method to reduce the cost of FPGA based systems. It means execution of logic in consecutive steps with reconfiguration taking…”
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Operation binding and scheduling for low power using constraint logic programming by Gruian, F., Kuchcinski, K.

“…Discusses high-level synthesis problems and solutions specific to low-power synthesis. This paper presents a method for power consumption minimization by…”
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Process scheduling for performance estimation and synthesis of hardware/software systems by Eles, P., Kuchcinski, K., Peng, Z., Doboli, A., Pop, P.

“…The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared…”
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Embedded system synthesis by timing constraints solving by Kuchcinski, K.

“…The paper presents an approach to embedded system synthesis which minimizes a system cost while implementing given timing requirements. The embedded system is…”
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A constraints programming approach for fabric cell synthesis by Wolinski, C., Kuchcinski, K.

“…This paper presents a novel method to generate optimized architecture of hardware processes implemented on "system on a programmable chip" (SoPC). The hardware…”
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Java to hardware compilation for non data flow applications by Andersson, P., Kuchcinski, K.

“…Java has proven to be a powerful language for software development. In this paper we show that it is also suitable for hardware compilation, making it an…”
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An efficient and economic partitioning approach for testability by Xinli Gu, Kuchcinski, K., Zebo Peng

“…This paper presents an RT level partitioning approach for sequential circuits described as data path and control part. The data path of a circuit is…”
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A constructive algorithm for memory-aware task assignment and scheduling by Szymanek, Radoslaw, Kuchcinski, Krzysztof

“…This paper presents a constructive algorithm for memory-aware task assignment and scheduling, which is a part of the prototype system MATAS. The algorithm is…”
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Synthesis of conditional behaviors using hierarchical conditional dependency graphs and constraint logic programming by Kuchcinski, K., Wolinski, C.

“…This paper presents a new high-level synthesis (HLS) approach which addresses the problem of synthesis of conditional behaviors. In proposed methodology, the…”
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Evaluation of SIMD architecture enhancement in embedded processors for MPEG-4 by Iranpour, A.R., Kuchcinski, K.

“…This paper presents our studies on the effects of using SIMD processor extension developed to enhance the processor performance for streaming applications. Our…”
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A constraints programming approach to communication scheduling on SoPC architectures by Wolinski, C., Kuchcinski, K., Gokhale, M.

“…This paper presents a method to obtain an optimized static schedule of CSP-like communications between a collection of concurrent hardware processes…”
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