A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology

The first multi-layer stacked 3D Flash memory was proposed as BiCS FLASH in 2007 [1]. Since then, memory bit density has grown rapidly due to the increase in the number of stacked layers from continuous 3D technology innovations. On the other hand, the multi-level-cell technology, which was initiall...

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Bibliographic Details
Published in:	2018 IEEE International Solid - State Circuits Conference - (ISSCC) pp. 336 - 338
Main Authors:	Maejima, Hiroshi, Kanda, Kazushige, Fujimura, Susumu, Takagiwa, Teruo, Ozawa, Susumu, Sato, Jumpei, Shindo, Yoshihiko, Sato, Manabu, Kanagawa, Naoaki, Musha, Junji, Inoue, Satoshi, Sakurai, Katsuaki, Morozumi, Naohito, Fukuda, Ryo, Shimizu, Yuui, Hashimoto, Toshifumi, Xu Li, Shimizu, Yuuki, Abe, Kenichi, Yasufuku, Tadashi, Minamoto, Takatoshi, Yoshihara, Hiroshi, Yamashita, Takahiro, Satou, Kazuhiko, Sugimoto, Takahiro, Kono, Fumihiro, Abe, Mitsuhiro, Hashiguchi, Tomoharu, Kojima, Masatsugu, Suematsu, Yasuhiro, Shimizu, Takahiro, Imamoto, Akihiro, Kobayashi, Naoki, Miakashi, Makoto, Yamaguchi, Kouichirou, Bushnaq, Sanad, Haibi, Hicham, Ogawa, Masatsugu, Ochi, Yusuke, Kubota, Kenro, Wakui, Taichi, Dong He, Weihan Wang, Minagawa, Hiroe, Nishiuchi, Tomoko, Hao Nguyen, Kwang-Ho Kim, Ken Cheah, Yee Koh, Feng Lu, Ramachandra, Venky, Rajendra, Srinivas, Choi, Steve, Payak, Keyur, Raghunathan, Namas, Georgakis, Spiros, Sugawara, Hiroshi, Seungpil Lee, Futatsuyama, Takuya, Hosono, Koji, Shibata, Noboru, Hisada, Toshiki, Kaneko, Tetsuya, Nakamura, Hiroshi
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-02-2018
Subjects:	Data transfer Flash memories Latches Programming Three-dimensional displays Throughput
Online Access:	Get full text
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Summary:	The first multi-layer stacked 3D Flash memory was proposed as BiCS FLASH in 2007 [1]. Since then, memory bit density has grown rapidly due to the increase in the number of stacked layers from continuous 3D technology innovations. On the other hand, the multi-level-cell technology, which was initially proposed for 2D Flash, has also been adopted to 3D Flash memories. The first 3b/cell 32-layer Flash was presented in 2015 [2], followed by a 48-layer one in 2016 [3], and a 64-layer one in 2017 [4,5]. This paper describes a 512Gb 3b/cell 3D Flash memory in a 96-word-line-layer BiCS FLASH technology. This work implements three key technologies to improve performance: (1) a string based start bias control scheme achieves a 7% shorter program time; (2) a smart V t -tracking read improves read retry performance by minimizing the tracking time and supporting a program suspend read function, and; (3) a low-pre-charge sense-amplifier bus scheme reduces both the power consumption and the data-transfer time between the sense amplifier (SA) and the data cache by half. Figure 20.1.1 shows the die micrograph and the summary of the key features of the chip.
ISSN:	2376-8606
DOI:	10.1109/ISSCC.2018.8310321