Search Results - "Kuang Yeu Hsieh"

Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices by Hsiao, Yi-Hsuan, Lue, Hang-Ting, Chen, Wei-Chen, Chang, Kuo-Pin, Shih, Yen-Hao, Tsui, Bing-Yue, Hsieh, Kuang-Yeu, Lu, Chih-Yuan

“…The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low…”
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A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method-Part I: Fundamental Theory and Applications to Study of the Trapped Charge Vertical Location and Capture Efficiency of SONOS-Type Devices by Lue, Hang-Ting, Du, Pei-Ying, Wang, Szu-Yu, Hsieh, Kuang-Yeu, Liu, Rich, Lu, Chih-Yuan

“…Using a recently developed gate-sensing and channel- sensing (GSCS) transient analysis method, we have studied the detailed charge-trapping behavior for…”
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Ultra-High Bit Density 3D NAND Flash-Featuring-Assisted Gate Operation by Hsiao, Yi-Hsuan, Lue, Hang-Ting, Chen, Wei-Chen, Tsui, Bing-Yue, Hsieh, Kuang-Yeu, Lu, Chih-Yuan

“…Lower saturation current flowing through the same cell twice is a major drawback of vertical stack array transistor architecture. A loading effect further…”
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Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices by HSU, Tzu-Hsuan, LUE, Hang-Ting, KING, Ya-Chin, HSIAO, Yi-Hsuan, LAI, Sheng-Chih, HSIEH, Kuang-Yeu, LIU, Rich, LU, Chih-Yuan

“…The physical model for field enhancement (FE) and the edge effects of body-tied FinFET charge-trapping NAND Flash devices are extensively studied in this…”
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Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model by Hang-Ting Lue, Tzu-Hsuan Hsu, Min-Ta Wu, Kuang-Yeu Hsieh, Liu, R., Chih-Yuan Lu

“…The reverse read method and second-bit effect of the 2-bit/cell nitride-trapping device are comprehensively studied by a quasi-two-dimensional (2-D) model…”
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A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method Part II: Study of the Intra-Nitride Behaviors and Reliability of SONOS-Type Devices by Pei-Ying Du, Hang-Ting Lue, Szu-Yu Wang, Tiao-Yuan Huang, Kuang-Yeu Hsieh, Liu, R., Chih-Yuan Lu

“…For the first time, we can directly investigate the charge transport and intra-nitride behaviors of SONOS-type devices by exploiting the gate-sensing and…”
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A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device by Hang-Ting Lue, Tzu-Hsuan Hsu, Yi-Hsuan Hsiao, Hong, S P, Wu, M T, Hsu, F H, Lien, N Z, Szu-Yu Wang, Jung-Yu Hsieh, Ling-Wu Yang, Yang, Tahone, Kuang-Chao Chen, Kuang-Yeu Hsieh, Chih-Yuan Lu

“…An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type…”
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Study of the Band-to-Band Tunneling Hot-Electron (BBHE) Programming Characteristics of p-Channel Bandgap-Engineered SONOS (BE-SONOS) by Wu, Min-Ta, Lue, Hang-Ting, Hsieh, Kuang-Yeu, Liu, Rich, Lu, Chih-Yuan

“…The band-to-band tunneling hot-electron (BBHE) programming characteristics of the 2 bit/cell p-channel bandgap-engineered…”
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Modeling and Characterization of Hydrogen-Induced Charge Loss in Nitride-Trapping Memory by YANG, Yi-Lin, CHANG, Chia-Hua, SHIH, Yen-Hao, HSIEH, Kuang-Yeu, HWU, Jenn-Gwo

“…This paper studies hydrogen diffusion in nitride-based Flash memory. Distorted capacitance-voltage ( C-V) curves were obtained when the programmed devices were…”
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A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for nand-Type Flash Memory by Tzu-Hsuan Hsu, Hang Ting Lue, Ya-Chin King, Jung-Yu Hsieh, Lai, E.-K., Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu

“…A body-tied FinFET bandgap engineered (BE)-silicon-oxide-nitride-oxide-silicon (SONOS) nand Flash device is successfully demonstrated for the first time…”
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Future challenges of flash memory technologies by Lu, Chih-Yuan, Hsieh, Kuang-Yeu, Liu, Rich

“…Flash memory application has seen explosive growth in recent years and this trend is likely to continue because new and more demanding applications are…”
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A transient analysis method to characterize the trap vertical location in nitride-trapping devices by Hang-Ting Lue, Yen-Hao Shih, Kuang-Yeu Hsieh, Liu, R., Chih-Yuan Lu

“…A new method to probe the trap vertical location for nitride-trapping devices is proposed. This method requires only measuring the time dependence of gate…”
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Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten Plugs by Lai, Erh-Kun, Chien, Wei-Chih, Chen, Yi-Chou, Hong, Tian-Jue, Lin, Yu-Yu, Chang, Kuo-Pin, Yao, Yeong-Der, Lin, Pang, Horng, Sheng-Fu, Gong, Jeng, Tsai, Shih-Chang, Lee, Ching-Hsiung, Hsieh, Sheng-Hui, Chen, Chun-Fu, Shih, Yen-Hao, Hsieh, Kuang-Yeu, Liu, Rich, Lu, Chih-Yuan

“…A complementary metal oxide semiconductor (CMOS)-compatible WO x based resistive memory has been developed. The WO x memory layer is made from rapid thermal…”
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Study of the Erase Mechanism of MANOS ( \hbox\hbox/\hbox/\hbox) Device by LAI, Sheng-Chih, LUE, Hang-Ting, HSIEH, Kuang-Yeu, LIU, Rich, LU, Chih-Yuan, HSIEH, Jong-Yu, YANG, Ming-Jui, CHIOU, Yan-Kai, WU, Chia-Wei, WU, Tai-Bor, LUO, Guang-Li, CHIEN, Chao-Hsin, LAI, Erh-Kun

“…The erase characteristics and mechanism of metal- Al 2 O 3 -nitride-oxide-silicon (MANOS) devices are extensively studied. We use transient analysis to…”
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Pulse- IV Characterization of Charge-Transient Behavior of SONOS-Type Devices With or Without a Thin Tunnel Oxide by Pei-Ying Du, Hang-Ting Lue, Szu-Yu Wang, Tiao-Yuan Huang, Kuang-Yeu Hsieh, Liu, R., Chih-Yuan Lu

“…The transient behavior of SONOS-type devices was investigated for the first time using pulse- IV technique. Three kinds of SONOS devices are studied: SONS…”
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A novel 1T2R self-reference physically unclonable function suitable for advanced logic nodes for high security level applications by Lin, Yu-Hsuan, Lee, Dai-Ying, Lee, Ming-Hsiu, Tseng, Po-Hao, Chen, Wei-Chen, Hsieh, Kuang-Yeu, Wang, Keh-Chung, Lu, Chih-Yuan

“…A self-reference resistive random-access memory (ReRAM)-based one-transistor, two-ReRAM (1T2R) physically unclonable function (PUF) is proposed to provide a…”
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study of incremental step pulse programming (ISPP) and STI edge effect of BE-SONOS NAND Flash by Hang-Ting Lue, Tzu-Hsuan Hsu, Szu-Yu Wang, Erh-Kun Lai, Kuang-Yeu Hsieh, Liu, R., Chih-Yuan Lu

“…Incremental-step-pulse programming (ISPP) is a key enabler for achieving tight V T distribution for MLC NAND Flash. The ISPP characteristics for BE-SONOS NAND…”
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A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm by Wang, Yun-Yuan, Lin, Yu-Hsuan, Lee, Dai-Ying, Lu, Cheng-Hsien, Wei, Ming-Liang, Tseng, Po-Hao, Lee, Ming-Hsiu, Hsieh, Kuang-Yeu, Wang, Keh-Chung, Lu, Chih-Yuan

“…We proposed an in-memory spin coupler based on the 55 nm NOR flash technology to tackle the combinatorial optimization problems. The high-density and…”
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A novel tite buffered Cu-GeSbTe/SiO2 electrochemical resistive memory (ReRAM) by Yu-Yu Lin, Feng-Ming Lee, Yi-Chou Chen, Wei-Chih Chien, Chiao-Wen Yeh, Kuang-Yeu Hsieh, Chih-Yuan Lu

“…A novel solid-electrolyte based electrochemical induced conductive bridge (CB) resistive memory (ReRAM) is fabricated and characterized. The new device…”
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Reliability Assessment for an In-3D-NAND Approximate Searching Solution by Tseng, Po-Hao, Lin, Yu-Hsuan, Lee, Feng-Min, Bo, Tian-Cih, Lee, Ming-Hsiu, Hsieh, Kuang-Yeu, Wang, Keh-Chung, Lu, Chih-Yuan

“…The reliability issues of an In-3D-NAND approximate searching system for Hamming distance computing are evaluated and solved by optimized high VT level,…”
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