Search Results - "Krstic, Angela"

Fast statistical timing analysis by probabilistic event propagation by Liou, Jing-Jia, Cheng, Kwang-Ting, Kundu, Sandip, Krstic, Angela

“…We propose a new statistical timing analysis algorithm, which produces arrival-time random variables for all internal signals and primary outputs for…”
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False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation by Jing-Jia Liou, Krstic, A., Wang, L.-C., Kwang-Ting Cheng

“…We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random…”
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Delay fault testing for VLSI circuits by Krstic, Angela

“…With the ever increasing speed of integrated circuits, violations of the performance specifications are becoming a major factor affecting the product quality…”
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Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability by Krstic, Angela, Cheng, Kwang-ting

“…Path delay fault model is the most suitable model for detectingdistributed manufacturing defects which can cause delayfaults. However, the number of paths in a…”
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Current directions in automatic test-pattern generation by Kwang-Ting Cheng, Krstic, A.

“…Test development automation tools, which automate dozens of tasks essential for developing adequate tests, generally fall into four categories: design for…”
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Estimation for maximum instantaneous current through supply lines for CMOS circuits by Yi-Min Jiang, Krstic, A., Kwang-Ting Cheng

“…We present new techniques for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. We investigate four different…”
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Delay defect diagnosis based upon statistical timing models - the first step [logic testing] by Krstic, A., Wang, L.-C., Kwang-Ting Cheng, Jing-Jia Liou, Abadir, M.S.

“…This paper defines a new diagnosis problem for diagnosing delay defects based upon statistical timing models. We illustrate the differences between delay…”
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Delay fault testing for VLSI circuits by Krstic, Angela

“…With the ever increasing speed of integrated circuits, violations of the performance specifications are becoming a major factor affecting the product quality…”
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Embedded software-based self-testing for SoC design by Kirstic, A., Lai, W.-C., Chen, L., Cheng, K.-T., Dey, S.

“…At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance,…”
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Test program synthesis for path delay faults in microprocessor cores by Wei-Cheng Lai, Krstic, A., Kwang-Ting Cheng

“…This paper addresses the problem of testing path delay faults in a microprocessor core using its instruction set. We propose to self-test a processor core by…”
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Generation of high quality tests for robustly untestable path delay faults by Kwang-Ting Cheng, Krstic, A., Hsi-Chuan Chen

“…In many designs a large portion of path delay faults is not robustly testable. In this paper, we investigate testing strategies for robustly untestable faults…”
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Primitive delay faults: identification, testing, and design for testability by Krstic, A., Kwang-Ting Cheng, Chakradhar, S.T.

“…We investigate two strategies to guarantee temporal correctness of a combinational circuit. We first propose a new technique to identify and test primitive…”
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Path selection and pattern generation for dynamic timing analysis considering power supply noise effects by Jing-Jia Liou, Krstic, A., Yi-Min Jiang, Kwang-Ting Cheng

“…Noise effects such as power supply and crosstalk can significantly affect the performance of deep submicron designs. These delay effects are highly input…”
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Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step by Krstic, Angela, Wang, Li-C., Cheng, Kwang-Ting, Liou, Jing-Jia, Abadir, Magdy S.

“…This paper defines a new diagnosis problem for diagnosing delay defects based upon statistical timing models. We illustrate the differences between the delay…”
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Diagnosis-based post-silicon timing validation using statistical tools and methodologies by Krstic, A., Wang, L.-C., Kwang-Ting Cheng, Mak, T.M.

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Delay testing considering power supply noise effects by Krstic, A., Yi-Min Jiang, Kwang-Ting Cheng

“…We propose a new delay test generation technique that can take into account the impact of the power supply noise on the signal propagation delays. This is…”
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False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation by Liou, Jing-Jia, Krstic, Angela, Wang, Li-C., Cheng, Kwang-Ting

“…We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random…”
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Post-layout Logic Restructuring For Performance Optimization by Yi-Min Jiang, Krstic, A., Kwang-Ting Cheng, Marek-Sadowska, M.

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Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects by Krstic, A., Yi-Min Jiang, Kwang-Ting Cheng

“…Noise effects such as power supply and crosstalk noise can significantly impact the performance of deep submicrometer designs. Existing delay testing and…”
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Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices by Jing-Jia Liou, Krstic, A., Yi-Ming Jiang, Kwang-Ting Cheng

“…The performance of deep submicron designs can be affected by various parametric variations, manufacturing defects, noise or modeling errors that are all…”
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