Search Results - "Krisch, K.S."

Thickness dependence of boron penetration through O/sub 2/- and N/sub 2/O-grown gate oxides and its impact on threshold voltage variation by Krisch, K.S., Green, M.L., Baumann, F.H., Brasen, D., Feldman, L.C., Manchanda, L.

“…We report on a quantitative study of boron penetration from p/sup +/ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in…”
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Low-temperature furnace-grown reoxidized nitrided oxide gate dielectrics as a barrier to boron penetration by Fang, H., Krisch, K.S., Gross, B.J., Sodini, C.G., Chung, J., Antoniadis, D.A.

“…Reoxidized nitrided oxide (ROXNOX) gate dielectrics can be used to block the diffusion of boron into the MOS channel region. However, fixed oxide charge…”
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Precursor ion damage and angular dependence of single event gate rupture in thin oxides by Sexton, F.W., Fleetwood, D.M., Shaneyfelt, M.R., Dodd, P.E., Hash, G.L., Schanwald, L.P., Loemker, R.A., Krisch, K.S., Green, M.L., Weir, B.E., Silverman, P.J.

“…No correlation was observed between single-event gate rupture (SEGR) and precursor damage by heavy-ion irradiation for 7-nm thermal and nitrided oxides…”
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Gate capacitance attenuation in MOS devices with thin gate dielectrics by Krisch, K.S., Bude, J.D., Manchanda, L.

“…As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate…”
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An optimized 850 degrees C low-pressure-furnace reoxidized nitrided oxide (ROXNOX) process by Gross, B.J., Krisch, K.S., Sodini, C.G.

“…The electrical characteristics of thin (10 nm) MOS gate dielectrics formed at 850 degrees C by low-pressure furnace nitridation of SiO/sub 2/ followed by an…”
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Ultra-thin gate dielectrics: they break down, but do they fail? by Weir, B.E., Silverman, P.J., Monroe, D., Krisch, K.S., Alam, M.A., Alers, G.B., Sorsch, T.W., Timp, G.L., Baumann, F., Liu, C.T., Ma, Y., Hwang, D.

“…We study breakdown in high-quality 2-7 nm gate dielectrics, and find that soft breakdown becomes more likely for thinner oxides and for oxides stressed at…”
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Substrate injection and crosstalk in CMOS circuits by Briaire, J., Krisch, K.S.

“…Substrate noise injection is evaluated, at the transistor level, for a 0.25 /spl mu/m CMOS technology, to determine the mechanisms that contribute to substrate…”
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R-4 Surface Control And Thin Gate Oxides by Taniguchi, K., Toriumi, A., Huber, D., Krisch, K.S.

“…Summary form only given. The electrical properties of thermally grown ultrathin Si02 layers on Si are a critical issue for the characteristics of deep…”
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Impact of boron diffusion through O/sub 2/ and N/sub 2/O gate dielectrics on the process margin of dual-poly low power CMOS by Krisch, K.S., Manchanda, L., Baumann, F.H., Green, M.L., Brasen, D., Feldman, L.C., Ourmazd, A.

“…This work evaluates the impact of boron penetration from p/sup +/-polysilicon on process margin and system performance. We experimentally demonstrate that…”
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The impact of nitrogen profile engineering on ultrathin nitrided oxide films for dual-gate CMOS ULSI by Hasegawa, E., Kawata, M., Ando, K., Makabe, M., Kitakata, M., Ishitani, A., Manchanda, L., Green, M.L., Krisch, K.S., Feldman, L.C.

“…We studied nitrogen profile engineering to make an ultra-thin silicon nitrided oxide (SiNO) film for 0.25 /spl mu/m dual-gate CMOS device applications. It was…”
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Effect of electronic corrections on the thickness dependence of thin oxide reliability by Alers, G.B., Oates, A.S., Monroe, D., Krisch, K.S., Weir, B.E.

“…The thickness dependence of constant voltage lifetime tests for thin oxides in the range of 50-125 /spl Aring/ show an apparent factor of 100 enhancement in…”
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Physics-based RF noise modeling of submicron MOSFETs by Donati, S., Alam, M.A., Krisch, K.S., Martin, S., Pinto, M.R., Vuong, H.H., Bonani, F., Ghione, G.

“…The Impedance Field Method (IFM) for physics-based noise modeling of electron devices is applied, for the first time, to evaluate the RF noise performance of…”
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A symmetric 0.25 /spl mu/m CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithography by Boulin, D.M., Mansfield, W.M., O'Connor, K.J., Bevk, J., Brasen, D., Cheng, M., Cirelli, R.A., Eshraghi, S.A., Green, M.L., Guinn, K.V., Hillenius, S.J., Ibbotson, D.E., Jacobson, D.C., Kim, Y.O., King, C.A., Kistler, R.C., Klemens, F.P., Krisch, K.S., Kornblit, A., Lee, J.T.C., Manchanda, L., McNevin, S.C., Moccio, S.V., Monroe, D.P., Ng, K.K., O'Malley, M.L., Rafferty, C.S., Schwartz, G.P., Vaidya, S., Weber, G.R., Feldman, L.C., Pinto, M.R., Itani, T., Tounai, T., Kasama, K., Miyamoto, H., Ikawa, E., Hasagawa, E., Ishitani, A., Ito, H., Horiuchi, T., Saito, S., Nakamae, M.

“…A 0.25 /spl mu/m coded feature CMOS technology has been developed for high-performance, low-power ASIC applications. Critical process features include 248 nm…”
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