Search Results - "Kossel, Marcel"

Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology by Kossel, Marcel, Francese, Pier Andrea, Brändli, Matthias, Ruffino, Andrea, Morf, Thomas

“…A method is presented for the design of high‐speed frequency dividers in which the divided output signals are phase aligned by means of a scheme based on…”
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Wide bandwidth room-temperature THz imaging array based on antenna-coupled MOSFET bolometer by Morf, Thomas, Klein, Bernhard, Despont, Michel, Drechsler, Ute, Kull, Lukas, Corcos, Dan, Elad, Danny, Kaminski, Noam, Pfeiffer, Ullrich R., Al Hadi, Richard, Keller, Hans M., Braendli, Matthias, Menolfi, Christian, Kossel, Marcel, Francese, Pier Andrea, Toifl, Thomas, Plettemeier, Dirk

“…We report on the design, fabrication and measurements of a new THz sensor concept based on an antenna-coupled MOSFET bolometer for room-temperature passive THz…”
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An active tagging system using circular-polarization modulation by Kossel, M.A., Kung, R., Benedickter, H., Biichtokd, W.

“…An active read/write microwave tagging system using circular-polarization modulation as a novel modulation scheme for radio-frequency identification systems is…”
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Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications by Bezerra, Pedro A. M., Krismer, Florian, Kolar, Johann W., Aljameh, Riduan K., Paredes, S., Heller, R., Brunschwiler, T., Francese, Pier A., Morf, T., Kossel, Marcel A., Braendli, M.

“…Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic…”
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A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS by Kull, Lukas, Toifl, Thomas, Schmatz, Martin, Francese, Pier Andrea, Menolfi, Christian, Brandli, Matthias, Kossel, Marcel, Morf, Thomas, Andersen, Toke Meyer, Leblebici, Yusuf

“…An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of…”
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A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET by Kull, Lukas, Luu, Danny, Menolfi, Christian, Brandli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Toifl, Thomas

“…A 24-72-GS/s 8-b time-interleaved analog-to-digital converter (ADC) is presented which exceeds 39-dB SNDR at low input frequency and 30-dB SNDR at Nyquist…”
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A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform by Lee, Jaewon, Jang, Seoyoung, Braendli, Matthias, Morf, Thomas, Kossel, Marcel, Francese, Pier-Andrea, Kim, Gain

“…This brief presents a 2-lane discrete multitone (DMT) wireline receiver (RX) with a far-end crosstalk (FEXT) cancellation and its implementation on the ZCU111…”
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A NRZ/PAM4 SST TX in 5nm FinFET CMOS with 3-tap FFE and 0.7pJ/b efficiency at 100 Gb/s PAM4 by Kossel, Marcel, Brandli, Matthias, Francese, Pier Andrea, Morf, Thomas

“…A source-series terminated (SST) transmitter (TX) for NRZ and PAM4 signaling across short reach channels (e.g., from a hub-chip to a processor die) is…”
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A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers by Kim, Donggeon, Choi, Yujin, Lee, Jaewon, Jang, Seoyoung, Song, Sungyu, Braendli, Matthias, Morf, Thomas, Kossel, Marcel, Francese, Pier-Andrea, Kim, Gain

“…This paper presents a novel digital decision feedback equalizer (DFE) design that can relax the feedback timing constraints for analog-to-digital converter…”
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Design of Time-Encoded Spiking Neural Networks in 7nm CMOS Technology by Widmer, Sandro, Kossel, Marcel, Cherubini, Giovanni, Wozniak, Stanislaw, Francese, Pier Andrea, Stanojevic, Ana, Brandli, Matthias, Frick, Klaus, Pantazi, Angeliki

“…In biologically inspired spiking neural networks (SNNs) neurons communicate by short pulses, called spikes. SNNs have the potential to be more power efficient…”
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A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation And Loading Profile Optimization On RFSoC by Lee, Jaewon, Jang, Seoyoung, Kim, Donggeon, Choi, Yujin, Yoon, Jong-Hyeok, Braendli, Matthias, Morf, Thomas, Kossel, Marcel, Francese, Pier-Andrea, Kim, Gain

“…This brief presents a discrete multi-tone (DMT) wireline transceiver (TRX) datapath and introduces the RFSoC-based real-time hardware platform to quickly sweep…”
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Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology by Widmer, Sandro, Kossel, Marcel, Cherubini, Giovanni, Woźniak, Stanislaw, Francese, Pier Andrea, Stanojevic, Ana, Brändli, Matthias, Frick, Klaus, Pantazi, Angeliki

“…In biologically inspired spiking neural networks (SNNs) neurons communicate by short pulses, called spikes. SNNs have the potential to be more power efficient…”
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A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET by Kim, Gain, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Burg, Andreas, Toifl, Thomas, Leblebici, Yusuf, Kull, Lukas, Luu, Danny, Braendli, Matthias, Menolfi, Christian, Francese, Pier-Andrea, Yueksel, Hazar, Aprile, Cosimo, Morf, Thomas

“…This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX…”
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Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS by Kull, Lukas, Pliva, Jan, Toifl, Thomas, Schmatz, Martin, Francese, Pier Andrea, Menolfi, Christian, Brandli, Matthias, Kossel, Marcel, Morf, Thomas, Andersen, Toke Meyer, Leblebici, Yusuf

“…A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100…”
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A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET by Luu, Danny, Kull, Lukas, Toifl, Thomas, Menolfi, Christian, Brandli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Yueksel, Hazar, Cevrero, Alessandro, Ozkaya, Ilter, Huang, Qiuting

“…A single-channel 12-bit SAR ADC achieving 250-340 MS/s and consuming 4.8-8.0 mW from 0.75 to 0.9 V is presented. At 300 MS/s, the ADC exhibits 61.6-dB peak…”
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An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels by Aprile, Cosimo, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Braendli, Matthias, Kossel, Marcel, Morf, Thomas, Kull, Lukas, Oezkaya, Ilter, Leblebici, Yusuf, Cevher, Volkan, Toifl, Thomas

“…This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme,…”
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A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform by Lee, Jaewon, Jang, Seoyoung, Choi, Yujin, Kim, Donggeon, Yonar, Serdar, Braendli, Matthias, Ruffino, Andrea, Morf, Thomas, Kossel, Marcel, Francese, Pier-Andrea, Kim, Gain

“…This brief presents an RFSoC-based functional verification platform for a 2-lane pulse amplitude modulation (PAM) transceiver (TRX) datapath supporting 4-level…”
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A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery by Andersen, Toke M., Krismer, Florian, Kolar, Johann W., Toifl, Thomas, Menolfi, Christian, Kull, Lukas, Morf, Thomas, Kossel, Marcel, Brandli, Matthias, Francese, Pier Andrea

“…Granular power delivery with per-core regulation for microprocessor power delivery has the potential to significantly improve the energy efficiency of future…”
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A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET by Ozkaya, Ilter, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Morf, Thomas, Brandli, Matthias, Kuchta, Daniel M., Kull, Lukas, Baks, Christian W., Proesel, Jonathan E., Kossel, Marcel, Luu, Danny, Lee, Benjamin G., Doany, Fuad E., Meghelli, Mounir, Leblebici, Yusuf, Toifl, Thomas

“…A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity,…”
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Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology by Chabane, Asma, Prathapan, Mridula, Mueller, Peter, Cha, Eunjung, Francese, Pier Andrea, Kossel, Marcel, Morf, Thomas, Zota, Cezar

“…In this work, we report the characterization and modeling of a 14 nm bulk FinFET technology from room-temperature down to 4.6 K. A cryogenic device model is…”
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