A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range

A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range

A 16 nm all-digital auto-calibrating adaptive clock distribution (ACD) enhances processor core performance and energy efficiency by mitigating the adverse effects of high-frequency supply voltage (V DD ) droops. The ACD integrates a tunable-length delay prior to the global clock distribution to prol...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits Vol. 51; no. 1; pp. 8 - 17
Main Authors: Bowman, Keith A., Raina, Sarthak, Bridges, J. Todd, Yingling, Daniel J., Nguyen, Hoan H., Appel, Brad R., Kolla, Yesh N., Jihoon Jeong, Atallah, Francois I., Hansquine, David W.
Format: Journal Article
Language:English
Published: IEEE 01-01-2016
Subjects:
Adaptive circuit
adaptive clock distribution
adaptive clocking
auto-calibration
Calibration
Circuits
clock-data compensation
Clocks
Delay
Delays
Electric potential
Failure
Microprocessors
Phase locked loops
Radiation detectors
self-calibration
Time factors
Tolerances
variation-tolerant design
Voltage
voltage droop
voltage variation
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Summary:A 16 nm all-digital auto-calibrating adaptive clock distribution (ACD) enhances processor core performance and energy efficiency by mitigating the adverse effects of high-frequency supply voltage (V DD ) droops. The ACD integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in core paths for multiple cycles after a droop occurs to provide a sufficient response time for clock frequency (F CLK ) adaptation. A dynamic variation monitor (DVM) detects the onset of the droop and interfaces with an adaptive control unit and clock divider to reduce F CLK in half at the TLD output to avoid path timing-margin failures. An auto-calibration circuit enables in-field, low-latency tuning of the DVM to accurately detect VDD droops across a wide range of operating conditions. The auto-calibration circuit maximizes the V DD -droop tolerance of the ACD while eliminating the overhead from tester calibration. From 109 die measurements across a wafer, the auto-calibrating ACD recovers a minimum of 90% of the throughput loss due to a 10% V DD droop in a conventional design for 100% of the dies. ACD measurements demonstrate simultaneous throughput gains and energy reductions ranging from 13% and 5% at 0.9 V to 30% and 13% at 0.6 V, respectively.
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ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2015.2473655