Search Results - "Koibuchi, Michihiro"

OPTWEB: A Lightweight Fully Connected Inter-FPGA Network for Efficient Collectives by Mizutani, Kenji, Yamaguchi, Hiroshi, Urino, Yutaka, Koibuchi, Michihiro

“…Modern FPGA accelerators can be equipped with many high-bandwidth network I/Os, e.g., 64 x 50 Gbps, enabled by onboard optics or co-packaged optics. Some…”
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Accelerating parallel data processing using optically tightly coupled FPGAs by Mizutani, Kenji, Yamaguchi, Hiroshi, Urino, Yutaka, Koibuchi, Michihiro

“…A cutting-edge field programmable gate array (FPGA) card can be equipped with high-bandwidth inputs and outputs by high-density optical integration, e.g.,…”
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Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects by Fujiwara, Ikki, Koibuchi, Michihiro, Matsutani, Hiroki, Casanova, Henri

“…Random network topologies have been proposed to create low-diameter, low-latency interconnection networks in large-scale computing systems. However, these…”
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Experimental Demonstration of Approximate Communication based on Radio-over-Fiber Systems by Ishimaru, Toshiki, Mihana, Takatomo, Koibuchi, Michihiro, Kawanishi, Tetsuya, Naruse, Makoto

“…The importance of multi-valued data transmission for improving communication throughput has become apparent with the explosive growth o communication and…”
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Distributed Shortcut Networks: Low-Latency Low-Degree Non-Random Topologies Targeting the Diameter and Cable Length Trade-Off by Truong, Nguyen T., Fujiwara, Ikki, Koibuchi, Michihiro, Khanh-Van Nguyen

“…Low communication latency becomes a main concern in highly parallel computers and supercomputers that reach millions of processing cores. Random network…”
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Packet Forwarding Cache of Commodity Switches for Parallel Computers by Hirasawa, Shoichi, Yamaki, Hayato, Koibuchi, Michihiro

“…Switch delay dominates communication latencies in interconnection networks, especially for short messages because switch delays are massive relative to the…”
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A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms by Flich, J., Skeie, T., Mejia, A., Lysne, O., Lopez, P., Robles, A., Duato, J., Koibuchi, M., Rokicki, T., Sancho, J. C.

“…Most standard cluster interconnect technologies are flexible with respect to network topology. This has spawned a substantial amount of research on…”
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Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs by Matsutani, Hiroki, Koibuchi, Michihiro, Ikebuchi, Daisuke, Usami, Kimiyoshi, Nakamura, Hiroshi, Amano, H

“…This paper proposes the ultrafine-grained run-time power gating of on-chip routers, in which the power supply to each router component (e.g., virtual-channel…”
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A case for random shortcut topologies for HPC interconnects by Koibuchi, M., Matsutani, H., Amano, H., Hsu, D. F., Casanova, H.

“…As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern…”
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High-Bandwidth Low-Latency Approximate Interconnection Networks by Fujiki, Daichi, Ishii, Kiyo, Fujiwara, Ikki, Matsutani, Hiroki, Amano, Hideharu, Casanova, Henri, Koibuchi, Michihiro

“…Computational applications are subject to various kinds of numerical errors, ranging from deterministic roundoff errors to soft errors caused by…”
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HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies by Kawano, Ryuta, Yasudo, Ryota, Matsutani, Hiroki, Koibuchi, Michihiro, Amano, Hideharu

“…Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve…”
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Tightly-Coupled Multi-Layer Topologies for 3-D NoCs by Matsutani, H., Koibuchi, M., Amano, H.

“…Three-dimensional network-on-chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for…”
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Highly available network design and resource management of SINET4 by Urushidani, Shigeo, Aoki, Michihiro, Fukuda, Kensuke, Abe, Shunji, Nakamura, Motonori, Koibuchi, Michihiro, Ji, Yusheng, Yamada, Shigeki

“…The Japanese academic backbone network has been providing a variety of multilayer network services to support a wide range of research and education activities…”
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A Case for Uni-directional Network Topologies in Large-Scale Clusters by Koibuchi, Michihiro, Totoki, Tomohiro, Matsutani, Hiroki, Amano, Hideharu, Chaix, Fabien, Fujiwara, Ikki, Casanova, Henri

“…Designing low-latency network topologies of switches is a key objective for next-generation large-scale clusters. Low latency is preconditioned on low hop…”
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Randomly Optimized Grid Graph for Low-Latency Interconnection Networks by Nakano, Koji, Takafuji, Daisuke, Fujita, Satoshi, Matsutani, Hiroki, Fujiwara, Ikki, Koibuchi, Michihiro

“…In this work we present randomly optimized grid graphs that maximize the performance measure, such as diameter and average shortest path length (ASPL), with…”
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SINET5: A low-latency and high-bandwidth backbone network for SDN/NFV Era by Kurimoto, Takashi, Urushidani, Shigeo, Yamada, Hiroshi, Yamanaka, Kenjiro, Nakamura, Motonori, Abe, Shunji, Fukuda, Kensuke, Koibuchi, Michihiro, Takakura, Hiroki, Yamada, Shigeki, Yusheng Ji

“…SINET5 is a new 100-Gbps-based academic backbone network, which started full-scale operations in April 2016. It uses multi-protocol label switching-transport…”
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Prediction router: Yet another low latency on-chip router architecture by Matsutani, H., Koibuchi, M., Amano, H., Yoshinaga, T.

“…Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core…”
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An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks by Jouraku, A., Koibuchi, M., Amano, H.

“…System area networks (SANs), which usually accept arbitrary topologies, have been used to connect hosts in PC clusters. Although deadlock-free routing is often…”
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Distributed Shortcut Networks: Layout-Aware Low-Degree Topologies Exploiting Small-World Effect by Nguyen, Van K., Le, Nhat T. X., Fujiwara, Ikki, Koibuchi, Michihiro

“…Low communication latency becomes a main concern in highly parallel computers and supercomputers. Random network topologies are best to achieve low average…”
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Layout-aware expandable low-degree topology by Truong, Nguyen T., Nguyen, Van K., Le, Nhat T. X., Fujiwara, Ikki, Chaix, Fabien, Koibuchi, Michihiro

“…System expandability becomes a major concern for highly-parallel computers and datacenters, because their number of nodes gradually increases year by year. In…”
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