Fine-Pitch RDL Integration for Fan-Out Wafer-Level Packaging

Fan-Out wafer-level packaging (FOWLP) semi-additive process (SAP) flow for three layers of redistribution layer (RDL) has been developed. Patched dicing lane design is adopted to improve RDL plating uniformity by ~40x, as measured by sheet resistance (Rs). We demonstrate warpage correction solution...

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Bibliographic Details
Published in:	2020 IEEE 70th Electronic Components and Technology Conference (ECTC) pp. 1126 - 1131
Main Authors:	Lianto, Prayudi, Tan, Chin Wei, Jie Peng, Qi, Jumat, Abdul Hakim, Dai, Xundong, Peter Fung, Khai Mum, Huei See, Guan, Chong, Ser Choong, Wee David Ho, Soon, Serine Soh, Siew Boon, Huang Sharon Lim, Seow, Calvin Chua, Hung Ming, Abdillah Haron, Ahmad, Kenneth Lee, Huan Ching, Zhang, Mingsheng, Ko, Zhi Hao, Ko San, Ye, Leong, Henry
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-06-2020
Subjects:	CMP Electromagnetic compatibility FOWLP leakage Plating Polymers RDL reliability Resistance Semiconductor device reliability undercut Wafer scale integration warpage
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Summary:	Fan-Out wafer-level packaging (FOWLP) semi-additive process (SAP) flow for three layers of redistribution layer (RDL) has been developed. Patched dicing lane design is adopted to improve RDL plating uniformity by ~40x, as measured by sheet resistance (Rs). We demonstrate warpage correction solution to improve pattern integrity despite tool handling limitations. We also demonstrate a CMP solution to improve 2/2um L/S RDL pattern integrity by >10x. We achieve RDL mechanical integrity through an integrated endpoint-detection-controlled wet etch solution to achieve <50nm undercut and extend SAP process to sub-2/2um L/S RDL. We also establish RDL electrical integrity by integrating wafer treatment solution after RDL formation to achieve line-to-line leakage current <0.1nA. Upon completion of wafer-level process, package assembly is carried out using SAC305 BGA onto PCB. Package integrity is examined using X-ray, followed by a progressive thermal cycling (TC) reliability test. RDL mechanical and electrical integrity is proven from the board-level reliability test where the RDL layers pass 1000 TC and failure occurs on the BGA level.
ISSN:	2377-5726
DOI:	10.1109/ECTC32862.2020.00181