Integrated circuits for particle physics experiments

Integrated circuits for particle physics experiments

High energy particle physics experiments investigate the nature of matter through the identification of subatomic particles produced in collisions of protons, electrons, or heavy ions which have been accelerated to very high energies. Future experiments will have hundreds of millions of detector cha...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits Vol. 35; no. 12; pp. 2018 - 2030
Main Authors: Snoeys, W., Anelli, G., Campbell, M., Cantatore, E., Faccio, F., Heijne, E.H.M., Jarron, P., Kloukinas, K.C., Marchioro, A., Moreira, P., Toifl, T., Wyllie, K.
Format: Journal Article
Language:English
Published: New York IEEE 01-12-2000
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Channels
Circuits
CMOS
Collision mitigation
Collisions
Detectors
Electronics
Experiments
Large Hadron Collider
Magnetic field measurement
Mesons
Particle beams
Particle measurements
Particle physics
Particle tracking
Pixels
Protons
R&D
Radiation detector circuits
Research & development
Timing
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Summary:High energy particle physics experiments investigate the nature of matter through the identification of subatomic particles produced in collisions of protons, electrons, or heavy ions which have been accelerated to very high energies. Future experiments will have hundreds of millions of detector channels to observe the interaction region where collisions take place at a 40 MHz rate. This paper gives an overview of the electronics requirements for such experiments and explains how data reduction, timing distribution, and radiation tolerance in commercial CMOS circuits are achieved for these big systems. As a detailed example, the electronics for the innermost layers of the future tracking detector, the pixel vertex detector, is discussed with special attention to system aspects. A small-scale prototype (130 channels) implemented in standard 0.25 /spl mu/m CMOS remains fully functional after a 30 Mrad(SiO/sub 2/) irradiation. A full-scale pixel readout chip containing 8000 readout channels in a 14 by 16 mm/sup 2/ area has been designed.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/4.890318