Search Results - "Klaassen, D. B. M."

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  1. 1

    A new recombination model for device simulation including tunneling by Hurkx, G.A.M., Klaassen, D.B.M., Knuvers, M.P.G.

    Published in IEEE transactions on electron devices (01-02-1992)
    “…A recombination model for device simulation that includes both trap-assisted tunneling (under forward and reverse bias) and band-to-band tunneling (Zener…”
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    Journal Article
  2. 2

    PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations by Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., Watts, J.

    Published in Solid-state electronics (2009)
    “…This paper reports recent progress in partially depleted (PD) SOI MOSFET modeling using a surface potential based approach. The new model is formulated within…”
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    Journal Article
  3. 3

    RF benchmark tests for compact MOS models by Smit, G D J, Scholten, A J, Klaassen, D B M

    “…Next to accurate fits of measurements, smoothness, and robustness, compact MOSFET models should ideally meet a large number of additional requirements. In this…”
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    Conference Proceeding
  4. 4

    Layout and spacer optimization for high-frequency low-noise performance in HBT's by Vanhoucke, T, Donkers, J J T M, Hurkx, G A M, Magnee, P H C, van Dalen, R, Egbers, J H, Klaassen, D B M

    “…In this work we study improvements of the high-frequency noise performance of HBT devices by means of layout and spacer optimization. Using an equivalent…”
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    Conference Proceeding
  5. 5

    RF-CMOS performance trends by Woerlee, P.H., Knitel, M.J., van Langevelde, R., Klaassen, D.B.M., Tiemeijer, L.F., Scholten, A.J., Zegers-van Duijnhoven, A.T.A.

    Published in IEEE transactions on electron devices (01-08-2001)
    “…The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices…”
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    Journal Article
  6. 6

    Modeling statistical dopant fluctuations in MOS transistors by Stolk, P.A., Widdershoven, F.P., Klaassen, D.B.M.

    Published in IEEE transactions on electron devices (01-09-1998)
    “…The impact of statistical dopant fluctuations on the threshold voltage V/sub T/ and device performance of silicon MOSFET's is investigated by means of…”
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    Journal Article
  7. 7

    The New CMC Standard Compact MOS Model PSP: Advantages for RF Applications by Scholten, A.J., Smit, G.D.J., De Vries, B.A., Tiemeijer, L.F., Croon, J.A., Klaassen, D.B.M., van Langevelde, R., Xin Li, Weimin Wu, Gildenblat, G.

    Published in IEEE journal of solid-state circuits (01-05-2009)
    “…The surface-potential-based compact MOS model PSP is reviewed with special emphasis to features of interest to analog and RF designers. Various aspects of the…”
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    Journal Article Conference Proceeding
  8. 8

    Investigation of power and linearity performance for low- and high-voltage SiGe HBTs by Dinh, T. V., Pijper, R., Vanhoucke, T., Gridelet, E., Klaassen, D. B. M.

    “…Linearity and power performance in both small-and large-signal region of low- and high-voltage SiGe HBTs has been investigated by on-wafer measurements and…”
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    Conference Proceeding
  9. 9

    An SiGe heterojunction bipolar transistor with very high open-base breakdown voltage by Dinh, T. V., Vanhoucke, T., Heringa, A., Al-Sa'di, M., Ivo, P., Klaassen, D. B. M., Magnee, P. H. C.

    “…An SiGe heterojunction bipolar transistor having a very high open-base breakdown voltage (BV CEO ), which is close to the hard breakdown voltage (BV CBO ), is…”
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    Conference Proceeding
  10. 10

    New fundamental insights into capacitance modeling of laterally nonuniform MOS devices by Aarts, A.C.T., van der Hout, R., Paasschens, J.C.J., Scholten, A.J., Willemsen, M.B., Klaassen, D.B.M.

    Published in IEEE transactions on electron devices (01-02-2006)
    “…In compact transistor modeling for circuit simulation, the capacitances of conventional MOS devices are commonly determined as the derivatives of terminal…”
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    Journal Article
  11. 11

    RF technology optimization by a fast method for linearity determination by Dinh, T. V., Vohra, A., Melai, J., Vanhoucke, T., Magnee, P. H. C., Klaassen, D. B. M.

    “…This paper introduces a new methodology to determine the small signal linearity of a device directly from 2-port Y-parameters. With that approach, a 10-fold…”
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    Conference Proceeding Journal Article
  12. 12

    Temperature and geometry dependence of the electrothermal instability of bipolar transistors by Scholten, A. J., Vanhoucke, T., Klaassen, D. B. M.

    “…We present an extensive investigation into the temperature and geometry dependence of the electrothermal instability of bipolar transistors. It is shown that…”
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    Conference Proceeding
  13. 13

    Comments on "A Physics-Based Analytic Solution to the MOSFET Surface Potential From Accumulation to Strong-Inversion Region" by Gildenblat, G.., Klaassen, D.B.M., McAndrew, C.C.

    Published in IEEE transactions on electron devices (01-08-2007)
    “…This paper points out inaccuracies and improper attribution to previous publications in the above paper by J. He (see ibid., vol.53, no.9, p.2008-16, Sep 2006)…”
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    Journal Article
  14. 14

    Fast noise prediction for process optimization using only standard DC and S-parameter measurements by Gridelet, E., Scholten, A. J., Klaassen, D. B. M., van Dalen, R., Pijper, R., Magnee, P. H. C., Tiemeijer, L. F., Dinh, V. T., Vanhoucke, T.

    “…This paper presents a method to select, amongst a series of devices differing on their process, the best device in terms of high-frequency noise…”
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    Conference Proceeding
  15. 15

    SiGe:C profile optimization for low noise performance by Magnee, P. H. C., van Dalen, R., Mertens, H., Vanhoucke, T., van Velzen, B., Huiskamp, P., Brunets, I., Donkers, J. J. T. M., Klaassen, D. B. M.

    “…Today's state-of-the-art SiGe BiCMOS processes show impressive high-frequency performance, with f T and f MAX exceeding 500GHz. However, SiGe can also offer…”
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    Conference Proceeding
  16. 16

    Extended high voltage HBTs in a high-performance BiCMOS process by Mertens, H., Magnee, P. H. C., Donkers, J. J. T. M., Gridelet, E., Huiskamp, P., Klaassen, D. B. M., Vanhoucke, T.

    “…An approach to integrate extended high voltage (EHV) npn SiGe heterojunction bipolar transitors (HBTs) in a high-performance BiCMOS process is presented. The…”
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    Conference Proceeding
  17. 17

    Wafer-specific centering of compact transistor model parameters for advanced technologies and models by De Vries, B., Scholten, A. J., Rommers, P. F. E., Stoutjesdijk, M., Klaassen, D. B. M.

    “…In the early stages of IC development, only very few circuit measurements are available. To build up confidence in the circuit simulations and to detect…”
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    Conference Proceeding
  18. 18

    Virtual technology for RF process and device development by Vanhoucke, T., Klaassen, D. B. M., Mertens, H., Donkers, J. J. T. M., Hurkx, G. A. M., Huizing, H. G. A., Magnee, P. H. C., Hijzen, E. A., van Dalen, R., Gridelet, E., Slotboom, J. W.

    “…The increasing complexity of modern technologies has made semiconductor process and device development challenging. A reduction in the number of experimental…”
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    Conference Proceeding
  19. 19

    PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs by Wu, W., Li, X., Gildenblat, G., Workman, G., Veeraraghavan, S., McAndrew, C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., Watts, J.

    “…This paper reports recent progress on partially depleted (PD) SOI modeling using a surface potential based approach. The new model, called PSP-SOI, is…”
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    Conference Proceeding
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