Minimization of Parasitic Inductances in SFQ Circuits Using Over- and Under-Ground Planes

We designed the single-flux-quantum (SFQ) circuits that were fabricating using the NEC 2.5 kA/cm 2 standard process that has four Nb layers. Before designing circuits with two ground planes, we estimated sheet inductances of the base and counter planes using simple rectangular-shape inductors. Estim...

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Bibliographic Details
Published in:	IEEE transactions on applied superconductivity Vol. 17; no. 2; pp. 462 - 465
Main Authors:	Myoren, H., Kishita, N., Taino, T., Takada, S.
Format:	Journal Article Conference Proceeding
Language:	English
Published:	New York, NY IEEE 01-06-2007 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	2-branch D-FF Applied sciences Circuit properties Circuit simulation Circuits Counting circuits Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electrical engineering. Electrical power engineering Electrodes Electronic circuits Electronics Exact sciences and technology Ground plane Inductance Inductors Integrated circuits Josephson junctions Large-scale systems Magnetic devices Minimization National electric code Niobium Optimization Over- and under-ground planes parasitic inductance Planes Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SFQ logic circuits Superconductivity Transformers and inductors Frequency dependence Superconducting logic circuits 2-branch D-FF Quantum logic Rectangular shape SFQ logic circuits parasitic inductance Inductor Over- and under-ground planes Quantum electronics Logic circuit Inductance Superconducting integrated circuits
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Summary:	We designed the single-flux-quantum (SFQ) circuits that were fabricating using the NEC 2.5 kA/cm 2 standard process that has four Nb layers. Before designing circuits with two ground planes, we estimated sheet inductances of the base and counter planes using simple rectangular-shape inductors. Estimated sheet inductance of the base plane was 0.75 of the original value for the circuits with only under-ground plane. For the counter plane, sheet inductance was estimated to be 0.55 of the original value. We designed a 2-branch D-FF gate and fabricated SFQ circuits including the 2-branch D-FF using the NEC standard process. Parasitic inductances of the counter layer in the 2-branch D-FF were effectively minimized using two ground planes and frequency dependences of the lower bias margin were improved.
Bibliography:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 ObjectType-Article-2 ObjectType-Feature-1
ISSN:	1051-8223 1558-2515
DOI:	10.1109/TASC.2007.898053