Search Results - "Kirsch, Paul D"

Benchmarking Transition Metal Dichalcogenide MOSFET in the Ultimate Physical Scaling Limit by Majumdar, Kausik, Hobbs, Chris, Kirsch, Paul D.

“…In this letter, we propose a nonplanar transition metal dichalcogenide (TMD) channel field effect transistor and explore its ballistic performance in the…”
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STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity by Majumdar, Kausik, Vivekanand, Saikumar, Huffman, Craig, Matthews, Ken, Tat Ngai, Chien Hao Chen, Baek, Rock Hyun, Wei Yip Loh, Rodgers, Martin, Stamper, Harlan, Gausepohl, Steven, Chang Yong Kang, Hobbs, Chris, Kirsch, Paul D.

“…We propose a very large scale integration compatible, modified transfer length method (TLM) structure, called sidewall TLM, to minimize the effect of spreading…”
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Impact of Fin Doping and Gate Stack on FinFET (110) and (100) Electron and Hole Mobilities by Akarvardar, K., Young, C. D., Baykan, M. O., Injo Ok, Tat Ngai, Kah-Wee Ang, Rodgers, M. P., Gausepohl, S., Majhi, P., Hobbs, C., Kirsch, P. D., Jammy, R.

“…Double-gate FinFET (110) (110) and (100) (100} electron mobility (μ e ) and hole mobility (μ h ) are experimentally investigated for the following: 1) a wide…”
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MoS2 Field-Effect Transistors With Graphene/Metal Heterocontacts by YUCHEN DU, LINGMING YANG, JINGYUN ZHANG, HAN LIU, MAJUMDAR, Kausik, KIRSCH, Paul D, YE, Peide D

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on-State Performance Enhancement and Channel-Direction-Dependent Performance of a Biaxial Compressive Strained \hbox\hbox Quantum-Well pMOSFET Along \langle \hbox \rangle and \langle \hbox \rangle Channel Directions by Se-Hoon Lee, Nainani, Aneesh, Jungwoo Oh, Kanghoon Jeon, Kirsch, Paul D, Majhi, Prashant, Register, Leonard Franklin, Banerjee, Sanjay K, Jammy, Raj

“…pMOSFET performance of high Ge content (~50%) biaxial compressive strained SiGe heterostructure channel pMOSFETs is characterized, and performance between 〈110…”
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Threshold Voltage Shift Due to Charge Trapping in Dielectric-Gated AlGaN/GaN High Electron Mobility Transistors Examined in Au-Free Technology by Johnson, Derek W., Lee, Rinus T. P., Hill, Richard J. W., Man Hoi Wong, Bersuker, Gennadi, Piner, Edwin L., Kirsch, Paul D., Harris, H. Rusty

“…We report on the investigation of the charge trapping characteristics of dielectric-gated AlGaN/GaN high electron mobility transistors (HEMTs) with atomic…”
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Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High- k/Metal Gate Stacks Directly on SiGe by Huang, J., Kirsch, P.D., Jungwoo Oh, Se Hoon Lee, Majhi, P., Harris, H.R., Gilmer, D.C., Bersuker, G., Dawei Heh, Chang Seo Park, Park, C., Hsing-Huang Tseng, Jammy, R.

“…This letter addresses mechanisms responsible for a high gate leakage current ( Jg ) and a thick interfacial layer in the surface channel SiGe pFET enabling…”
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Field-Effect Transistors With Graphene/Metal Heterocontacts by Yuchen Du, Lingming Yang, Jingyun Zhang, Han Liu, Majumdar, Kausik, Kirsch, Paul D., Ye, Peide D.

“…For the first time, n-type few-layer MoS 2 field-effect transistors (FETs) with graphene/Ti as the heterocontacts have been fabricated, showing more than…”
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Mapping Defect Density in MBE Grown Epitaxial Layers on Si Substrate Using Esaki Diode Valley Characteristics by Majumdar, Kausik, Thomas, Paul, Wei-Yip Loh, Pui-Yee Hung, Matthews, Ken, Pawlik, David, Romanczyk, Brian, Filmer, Matthew, Gaur, Abhinav, Droopad, Ravi, Rommel, Sean L., Hobbs, Chris, Kirsch, Paul D.

“…Growing good quality III-V epitaxial layers on Si substrate is of utmost importance to produce next generation high-performance devices in a cost effective…”
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Improved ge surface passivation with ultrathin SiOx enabling high-mobility surface channel pMOSFETs featuring a HfSiO/WN gate stack by JOSHI, Sachin, KRUG, Cristiano, JAMMY, Raj, LEE, Jack C, BANERJEE, Sanjay K, HEH, Dawei, HOON JOO NA, HARRIS, Harlan R, JUNG WOO OH, KIRSCH, Paul D, MAJHI, Prashant, BYOUNG HUN LEE, TSENG, Hsing-Huang

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Impact of Millisecond Flash-Assisted Rapid Thermal Annealing on SiGe Heterostructure Channel pMOSFETs With a High-k/Metal Gate by Se-Hoon Lee, Majhi, P., Ferrer, D. A., Pui-Yee Hung, Huang, J., Oh, J., Wei-Yip Loh, Sassman, B., Byoung-Gi Min, Hsing-Huang Tseng, Harris, R., Bersuker, G., Kirsch, P. D., Jammy, R., Banerjee, S. K.

“…Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels…”
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Improved 20nm device yield and gate dielectric integrity with optimized aluminum metal fill process by Williams, David, Bordelon, Clint, Drizlikh, Sergei, Kirsch, Paul D., Lam, Kin-Sang, Coppala, Paul, Guerassio, Ian, Hira, Nikhil Bharat, Trigno, Steven, Nester, Paul, Paulsen, Ryan, Patel, Anuj, Kim, Jun-Han, Park, Jungmin, Kim, Taegyun, Kang, Hee Sung, Seo, Jinho, An, Chulwan, Wang, Sunjong

“…Titanium-aluminum (TiAl) alloys are the industry standard source for work function tuning of High-K nMOS transistors in the gate-last process architecture…”
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The Effect of Nanoscale Nonuniformity of Oxygen Vacancy on Electrical and Reliability Characteristics of HfO2 MOSFET Devices by PARK, Hokyung, JO, Minseok, HWANG, Hyunsang, CHOI, Hyejung, HASAN, Musarrat, CHOI, Rino, KIRSCH, Paul D, CHANG YOUNG KANG, BYOUNG HUN LEE, KIM, Tae-Wook, LEE, Takhee

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Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs by Seung-Chul Song, Zhibo Zhang, Huffman, C., Sim, J.H., Sang Ho Bae, Kirsch, P.D., Majhi, P., Rino Choi, Moumen, N., Byoung Hun Lee

“…Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a…”
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The Effect of Nanoscale Nonuniformity of Oxygen Vacancy on Electrical and Reliability Characteristics of \hbox MOSFET Devices by Hokyung Park, Minseok Jo, Hyejung Choi, Hasan, M., Rino Choi, Kirsch, P.D., Chang Young Kang, Byoung Hun Lee, Tae-Wook Kim, Takhee Lee, Hyunsang Hwang

“…To understand the influence of oxygen vacancies in on the electrical and reliability characteristics, we have investigated area-dependent leakage-current…”
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KaleidaGraph:  Graphing and Data Analysis. Version 3.5 for Windows Synergy Software, 2457 Perkiomen Ave., Reading, PA 19606-2049. www.Synergy.com. $155.00 by Kirsch, Paul D, Ekerdt, John G

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Characteristics of a band edge p-channel metal-oxide-semiconductor field effect transistors fabricated with a high-k /WAlx/TiSiN gate stack by Park, Chang Seo, Hussain, Muhamad M., Bersuker, Gennadi, Kirsch, Paul D., Jammy, Raj

“…A metal/high-k gate stack with a p-type band edge effective work function (EWF) of about 5.0 eV is demonstrated using a thin WAlx capping layer. The WAlx stack…”
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Threshold Voltage Shift Due to Charge Trapping in Dielectric-Gated AlGaN/GaN High Electron Mobility Transistors Examined in Au-Free Technology : GaN ELECTRONIC DEVICES by JOHNSON, Derek W, LEE, Rinus T. P, HILL, Richard J. W, MAN HOI WONG, BERSUKER, Gennadi, PINER, Edwin L, KIRSCH, Paul D, HARRIS, H. Rusty

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Contact resistance improvement by dielectric breakdown in semiconductor-dielectric-metal contact by Majumdar, Kausik, Hobbs, Chris, Matthews, Ken, Chen, Chien-Hao, Ngai, Tat, Yong Kang, Chang, Bersuker, Gennadi, Vivekanand, Saikumar, Rodgers, Martin, Gausepohl, Steven, Kirsch, Paul D., Jammy, Raj

“…We propose an approach for reduction of the contact resistance by inducing dielectric breakdown in a Si-dielectric-metal contact stack. We observe a 36%…”
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Characteristics of a band edge p-channel metal-oxide-semiconductor field effect transistors fabricated with a high-k / WAl x /TiSiN gate stack by Park, Chang Seo, Hussain, Muhamad M., Bersuker, Gennadi, Kirsch, Paul D., Jammy, Raj

“…A metal/high-k gate stack with a p-type band edge effective work function (EWF) of about 5.0 eV is demonstrated using a thin WAl x capping layer. The WAl x…”
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