Search Results - "King-Jien Chui"

n-MOSFET With Silicon-Carbon Source/Drain for Enhancement of Carrier Transport by King-Jien Chui, Kah-Wee Ang, Balasubramanian, N., Ming-Fu Li, Samudra, G.S., Yee-Chia Yeo

“…A novel strained-silicon (Si) n-MOSFET with 50-nm gate length is reported. The strained n-MOSFET features silicon-carbon (Si 1-y C y ) source and drain (S/D)…”
Get full text

Performance Enhancement in Uniaxial Strained Silicon-on-Insulator N-MOSFETs Featuring Silicon-Carbon Source/Drain Regions by Kah-Wee Ang, King-Jien Chui, Chih-Hang Tung, Balasubramanian, N., Samudra, G.S., Yee-Chia Yeo

“…We report the demonstration of a novel strained silicon-on-insulator N-MOSFET featuring silicon-carbon (Si 1-y C y ) source and drain (S/D) regions, tantalum…”
Get full text

Analog switching characteristics in TiW/Al2O3/Ta2O5/Ta RRAM devices by Song, Wendong, Wang, Weijie, Lee, Hock Koon, Li, Minghua, Zhuo, Victor Yi-Qian, Chen, Zhixian, Chui, King Jien, Liu, Jen-Chieh, Wang, I.-Ting, Zhu, Yao, Singh, Navab

“…In this letter, we report analog switching characteristics in an analog resistive random access memory device based on a TiW/Al2O3/Ta2O5/Ta stack. For this…”
Get full text

Enhanced Strain Effects in 25-nm Gate-Length Thin-Body nMOSFETs With Silicon-Carbon Source/Drain and Tensile-Stress Liner by Kah-Wee Ang, King-Jien Chui, Chih-Hang Tung, Balasubramanian, N., Ming-Fu Li, Samudra, G.S., Yee-Chia Yeo

“…We report the demonstration of 25-nm gate-length L G strained nMOSFETs featuring the silicon-carbon source and drain (Si 1-y C y S/D) regions and a thin-body…”
Get full text

Demonstration and Challenges of Through Si Interposer (TSI) with 5-layer Frontside Cu Metal and 2-layer Backside Cu RDL by Tseng, Ya-Ching, Chui, King-Jien

“…Through Silicon Interposer (TSI) is a promising technology to realize 2.5D/3D platform for high-performance computing like artificial intelligence (AI) and…”
Get full text

Process and Integration Challenges for Via Last TSV (from top) on Functional LNA SOI wafers for 3D Heterogeneous chiplet integration by Wang, Xiangyu, Rotaru, Mihai Dragos, Haitao, Yu, Jonq, Mingchinq, Chong, Chai Tai, Chui, King-Jien

“…In our previous work, we discussed the demonstration of 10µm x 100µm Via-Last TSV (from top) fabrication on a blanket SOI Wafer, as illustrated in Fig 1(a)…”
Get full text

Investigation of SnAg Superconductivity as Solder Material for Cryogenic Packaging by Ng, Yong Chyn, Li, Hongyu, Jaafar, Norhanani Binte, Cheow Siong Lee, Rainer, Huang, Ding, Lau, Chit Siong, Eng Johnson Goh, Kuan, Chui, King-Jien

“…The drive towards quantum computing has prompted a need for advanced packaging technologies capable of withstanding the harsh cryogenic environments in which…”
Get full text

Indium-based Flip-chip Interconnect for Cryogenic Packaging by Jaafar, Norhanani Binte, Hongyu, Li, Choong, Chong Ser, Yong Chyn, Ng, Huang, Ding, Lau, Chit Siong, Goh, Kuan Eng Johnson, Chui, King-Jien

“…Flip-chip die attachment manufacturing has seen a dramatic increase in recent years due to improvements in electrical performance and reduced form-factor…”
Get full text

Evaluation of Low Temperature Inorganic Dielectric Materials for Hybrid Bonding Applications by Kumar, Mishra Dileep, Nagendra Sekhar, Vasarla, Choong, Chong Ser, Chandra Rao, B.S.S., Chui, King-Jien, Rao, Vempati Srinivasa

“…High-bandwidth memory (HBM) market is witnessing huge demand for high performance computing. Vertical/3D stacking of memory chips using hybrid bonding is a…”
Get full text

Strained Thin-Body p-MOSFET With Condensed Silicon-Germanium Source/Drain for Enhanced Drive Current Performance by Kah-Wee Ang, King-Jien Chui, Madan, A., Lai-Yin Wong, Chih-Hang Tung, Balasubramanian, N., Ming-Fu Li, Samudra, G.S., Yee-Chia Yeo

“…Strained p-MOSFETs with silicon-germanium (SiGe) source and drain (S/D) stressors were fabricated on thin-body silicon-on-insulator (SOI) substrate using a…”
Get full text

Two-Phase Liquid Cooling for High-Power Microelectronics via Embedded Micro-Pin Fin Heat Sink by Feng, Huicheng, Tang, Gongyue, Zhang, Xiaowu, Lau, Boon Long, Jong, Ming Chinq, Au, Keng Yuen Jason, Ong, Jun Wei Javier, Chui, King Jien, Li, Jun, Li, Hongying, Vinh Le, Duc, Lou, Jing

“…Two-phase liquid cooling can achieve high heat flux and is therefore a key method for heat dissipation of high-power microelectronics. In this study, we…”
Get full text

Strained-SOI n-Channel Transistor With Silicon-Carbon Source/Drain Regions for Carrier Transport Enhancement by King-Jien Chui, Kah-Wee Ang, Hock-Chun Chin, Chen Shen, Lai-Yin Wong, Chih-Hang Tung, Balasubramanian, N., Ming Fu Li, Samudra, G.S., Yee-Chia Yeo

“…A novel 80 nm gate length strained-Si n-channel transistor structure with lattice-mismatched source and drain (S/D) formed on thin-body silicon-on-insulator…”
Get full text

Room Temperature Plasma-Enhanced Niobium-Niobium Wafer Bonding for 3D Integration of Superconducting Interconnects for Quantum Processing by Kiat Goh, Simon Chun, Hemanth Kumar, Cheemalamarri, Hu, Liangxing, Shervonne, Woon, Jaafar, Norhanani, Khoon Sherry, Yap Lee, Huang, Ding, Lau, Chit Siong, Kumar Karuppannan, Senthil, Li, Hongyu, Tan, Chuan Seng, Chui, King-Jien

“…Quantum computing relies on a blend of superposition and entanglement phenomena of qubit devices to solve problems. It promises unparalleled computational…”
Get full text

CMOS-Compatible Fine Pitch Al-Al Bonding by Cheemalamarri, Hemanth Kumar, Varghese, Binni, Jaibir, Sharma, Hongyu, Li, S, Chandra Rao S, Singh, Navab, Rao, Vempati Srinivasa, Chui, King-Jien

“…The metal-metal bonding has become more promising for fine-line hermitic sealing and electronic packaging applications. Even though aluminum has CMOS…”
Get full text

Demonstration of a CMOS-Compatible Superconducting Cryogenic Interposer for Advanced Quantum Processors by Chui, King-Jien, Li, Hongyu, Ng, Yong Chyn, Lau, Chit Siong, Goh, K. E. J., Huang, D., Tseng, Ya-Ching, Chen, J. K., Yu, H., Jaafar, B. N., Lin, H., Varghese, B.

“…An advanced quantum processor requires millions of qubits but is at present limited in scalability due to limitations in the wiring of qubits. A 2.5D silicon…”
Get full text

A Precise Wafer Thinning Integration Process for nano-TSV Formation by Tseng, Ya-Ching, Kiat Goh, Simon Chun, Darshini, Senthilkumar, Venkataraman, Nandini, Sundaram, Arvind, Khang, Tew Chin, Ok, Yoo Jae, Chui, King-Jien

“…This paper proposes the use of a Silicon-On-Insulator (SOI) substrate to control the final Si thickness on the substrate. After direct wafer-to-wafer bonding…”
Get full text

Electrical Characterization of CMP-Less Via-Last TSV under Reliability Stress Conditions by King Jien Chui, Mingbin Yu

“…Via-Last (VL) Through Silicon Via (TSV) is being pursued for its added benefits of process flow simplicity, lower cost and integration flexibility. A novel,…”
Get full text

SDODEL MOSFET for performance enhancement by King Jien Chui, Samudra, G.S., Yee-Chia Yeo, Kheng-Chok Tee, Leong, K.-W., Kian Meng Tee, Benistant, F., Lap Chan

“…A high-energy, low-dose implant of the source/drain (S/D) doping type is introduced after the gate definition step to form doped regions beneath and separated…”
Get full text

A Novel Method for Air-Gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ) by King-Jien Chui, Woon Leng Loh, Xiangyu Wang, Zhaohui Chen, Mingbin Yu

“…Significant stress is induced in the crystalline Si area around a Cu-filled Through Silicon Via (TSV) due to the large mismatch in the co-efficient of thermal…”
Get full text

Under-Bump Metallization Contact Resistance ( R ) Characterization at 10- \mu \text Polymer Passivation Opening by Lianto, Prayudi, King-Jien Chui, Bhushan, Bharat, Chua, H. M. Calvin, Leijun Tang, Chandra Rao, B. S. S., Xin Wang, Ai Long Wu, Yu Gu, Guan Huei See, Sundarrajan, Arvind

“…Under-bump metallization R c is a critical metric for high-density interconnect in electronic devices. We developed a test vehicle to characterize the impact…”
Get full text