Search Results - "Kimijima, H"

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating by Ohguro, T., Sugiyama, N., Imai, S., Usuda, K., Saito, M., Yoshitomi, T., Ono, M., Kimijima, H., Momose, H.S., Katsumata, Y., Iwai, H.

“…Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to…”
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A study of flicker noise in n- and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regime by Momose, H.S., Kimijima, H., Ishizuka, S., Miyahara, Y., Ohguro, T., Yoshitomi, T., Morifuji, E., Nakamura, S., Morimoto, T., Katsumata, Y., Iwai, H.

“…Flicker noise characteristics of 1.5 nn direct-tunneling gate oxide n- and pMOSFETs have been investigated It was confirmed that in the shorter gate length…”
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Process induced damage on RFCMOS by Morifuji, E., Ohguro, T., Yoshitomi, T., Kimijima, H., Morimoto, T., Momose, H.S., Katsumata, Y., Iwai, H.

“…We have investigated the correlation between process induced damage and RF analog characteristics. Vth matching, fmax, and NFmin were analyzed using mass data…”
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On-chip spiral inductors with diffused shields using channel-stop implant by Yoshitomi, T., Sugawara, Y., Morifuji, E., Ohguro, T., Kimijima, H., Morimoto, T., Momose, H.S., Katsumata, Y., Iwai, H.

“…We investigated the Diffused shield Under the Oxide (DUO) for the first time. DUO is an extremely shallow diffusion layer in the n-well under the field oxide…”
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Effects of temperature, sowing depth and soil hardness on seedling establishment and yield of Cambodian rice [Oryza sativa] direct-seeded in flood paddy fields by Tong, L.(Tokyo Univ. of Agriculture and Technology, Fuchu (Japan)), Yoshida, T, Maeda, T, Kimijima, H

“…Rice is The Most Important Crop For Supporting Cambodian Economy, However The Cultivated Area is Limited Due To The Rice Production System. Rice is…”
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An 0.18-/spl mu/m CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs by Ohguro, T., Naruse, H., Sugaya, H., Morifuji, E., Nakamura, S., Yoshitomi, T., Morimoto, T., Kimijima, H., Sasaki Momose, H., Katsumata, Y., Iwai, H.

“…An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs…”
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An 0.18-mu m CMOS for mixed digital and analog applications withzero-volt-V(th) epitaxial-channel MOSFETs by Ohguro, T, Naruse, H, Sugaya, H, Morifuji, E, Nakamura, S, Yoshitomi, T, Morimoto, T, Kimijima, H, Sasaki Momose, H, Katsumata, Y, Iwai, H

“…An 0.18-mum CMOS technology with multi-V(th)s for mixed high-speed digital and RF-analog applications has been developed. The V (th)s of MOSFETs for digital…”
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An 0.18-μm CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs by Ohguro, T., Naruse, H., Sugaya, H., Morifuji, E., Nakamura, S., Yoshitomi, T., Morimoto, T., Kimijima, H., Sasaki Momose, H., Katsumata, Y., Iwai, H.

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Deposition and characterization of ZnxMg1−xS thin films on amorphous substrates by Kimijima, Hideaki, Kitagawa, Masahiko, Inoue, Ryou, Shiraishi, Nami, Hoashi, Masaharu, Ichino, Kunio, Kobayashi, Hiroshi

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0.18- mu m CMOS for mixed digital and analog applications with zero-volt-V sub(th) epitaxial-channel MOSFET's by Ohguro, Tatsuya, Naruse, Hiroshi, Sugaya, Hiroyuki, Morifuji, Eiji, Nakamura, Sinichi, Yoshitomi, Takashi, Morimoro, Toyota, Kimijima, Hideki, Momose, Hisayo Sasaki, Katsumata, Yasuhiro, Iwai, Hiroshi

“…An 0.18- mu m CMOS technology with multi-V sub(th)'s for mixed high-speed digital and RF-analog applications has been developed. The V sub(th)'s of MOSFET's…”
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A study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation by Yoshitomi, Takashi, Kimijima, Hideki, Ishizuka, Shinnichiro, Miyahara, Yasunori, Ohguro, Tatsuya, Morifuji, Eiji, Morimoto, Toyota, Sasaki Momose, Hisayo, Katsumata, Yasuhiro, Iwai, Hiroshi

“…A self-Aligned Doped Channel (SADC) is proposed and investigated for the first time. In the SADC process, the channel doping process is carried out by using…”
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A high performance 0.15 μm buried channel pMOSFET with extremely shallow counter doped channel region using solid phase diffusion by Yoshitomi, Takashi, Oguma, Hideki, Ohguro, Tatsuya, Morifuji, Eiji, Morimoto, Toyota, Momose, Hisayo Sasaki, Kimijima, Hideki, Katsumata, Yasuhiro, Iwai, Hiroshi

“…A new process for a counter-doped region suitable for a 0.15 μm (gate length) buried channel (BC) pMOSFET is presented. At present serious short-channel…”
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Deposition and characterization of ZnxMg1-xS thin films on amorphous substrates by KIMIJIMA, H, KITAGAWA, M, INOUE, R, SHIRAISHI, N, HOASHI, M, ICHINO, K, KOBAYASHI, H

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Single-electron-tunneling effect in nanoscale granular microbridges by YOSHIKAWA, N, KIMIJIMA, H, MIURA, N, SUGAHARA, M

“…The single-electron-tunneling (SET) effect in a nanoscale granular microbridge, which consists of a two-dimensional array of small intergrain tunnel junctions,…”
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Fabrication of Pd nanostructures with scanning tunneling microscope by FUKUZAWA, H, KIMIJIMA, H, YOSHIKAWA, N, SUGAHARA, M

“…Nanometer-scale mounds were fabricated on Pd thin films with a scanning tunneling microscope (STM) by applying a voltage pulse to a Pd tip. Regardless of the…”
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A low power 40nm CMOS technology featuring extremely high density of logic (2100kGate/mm2) and SRAM (0.195μm2) for wide range of mobile applications with wireless system by Watanabe, R., Oishi, A., Sanuki, T., Kimijima, H., Okamoto, K., Fujita, S., Fukui, H., Yoshida, K., Otani, H., Morifuji, E., Kojima, K., Inohara, M., Igrashi, H., Honda, K., Yoshimura, H., Nakayama, T., Miyake, S., Hirai, T., Iwamoto, T., Nakahara, Y., Kinoshita, K., Morimoto, T., Kobayashi, S., Kyoh, S., Ikeda, M., Imai, K., Iwai, M., Nakamura, N., Matsuoka, F.

“…Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive…”
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RF modelling for 0.1um gate length MOSFETs by Morifuji, E., Ohguro, T., Kimijima, H., Yoshitomi, T., Momose, H.S., Katsumata, Y., Ishimaru, K., Matsuoka, F., Kinugawa, M., Iwai, H.

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Future perspective and scaling down roadmap for RF CMOS by Morifuji, E., Momose, H.S., Ohguro, T., Yoshitomi, T., Kimijima, H., Matsuoka, F., Kinugawa, M., Katsumata, Y., Iwai, H.

“…The concept of future scaling-down for RF CMOS technology has been investigated in terms of f/sub T/, f/sub max/, RF noise, linearity, and matching…”
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Future perspective and scaling down roadmap for RF CMOS by Morifuji, E., Momose, H.S., Ohguro, T., Yoshitomi, T., Kimijima, H., Matsuoka, F., Kinugawa, M., Katsumata, Y., Iwai, H.

“…Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation…”
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0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technology by Ohguro, T., Naruse, H., Sugaya, H., Kimijima, H., Morifuji, E., Yoshitomi, T., Morimoto, T., Momose, H.S., Katsumata, Y., Iwai, H.

“…We introduce a 0.12 /spl mu/m nMOS technology with multi-Vth's for mixed high-speed digital and RF-analog applications. Though basically device parameter was…”
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