Search Results - "Kim, Jae‐Joon"

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  1. 1

    Negative Transconductance Heterojunction Organic Transistors and their Application to Full‐Swing Ternary Circuits by Yoo, Hocheon, On, Sungmin, Lee, Seon Baek, Cho, Kilwon, Kim, JaeJoon

    Published in Advanced materials (Weinheim) (01-07-2019)
    “…Multivalued logic (MVL) computing could provide bit density beyond that of Boolean logic. Unlike conventional transistors, heterojunction transistors (H‐TRs)…”
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    Journal Article
  2. 2

    Mobileware: Distributed Architecture With Channel Stationary Dataflow for MobileNet Acceleration by Ryu, Sungju, Jang, Jaeyong, Oh, Youngtaek, Kim, Jae-Joon

    “…The depthwise separable convolution, a key feature of the MobileNet models, has a different input reuse pattern from the conventional standard convolution, and…”
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  3. 3

    V-LSTM: An Efficient LSTM Accelerator using Fixed Nonzero-Ratio Viterbi-Based Pruning by Kim, Taesu, Ahn, Daehyun, Lee, Dongsoo, Kim, Jae-Joon

    “…Long Short-Term Memory (LSTM) has been widely adopted in tasks with sequence data, such as speech recognition and language modeling. LSTM brought significant…”
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  4. 4

    Efficient Convolutional Processing of Spiking Neural Network With Weight-Sharing Filters by Song, Seunghwan, Jeon, Bosung, Kim, Munhyeon, Kim, Jae-Joon

    Published in IEEE electron device letters (01-06-2023)
    “…The importance of implementing an efficient convolutional neural network (CNN) is increasing. A weight-sharing spiking CNN inference system (WS-SCNN) employing…”
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  5. 5

    BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks by Ryu, Sungju, Kim, Hyungjun, Yi, Wooseok, Kim, Eunhwan, Kim, Yulhwa, Kim, Taesu, Kim, Jae-Joon

    Published in IEEE journal of solid-state circuits (01-06-2022)
    “…We introduce an area/energy-efficient precision-scalable neural network accelerator architecture. Previous precision-scalable hardware accelerators have…”
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  6. 6

    Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks by Ryu, Sungju, Oh, Youngtaek, Kim, Jae-Joon

    “…Binary neural networks (BNNs) largely reduce the memory footprint and computational complexity, so they are gaining interests on various mobile applications…”
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  7. 7

    Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations by Ryu, Sungju, Koo, Jongeun, Kim, Wook, Kim, Yonghwan, Kim, Jae-Joon

    Published in IEEE journal of solid-state circuits (01-07-2021)
    “…We introduce a new clocking approach for digital systems to achieve better resilience to process, voltage, and temperature (PVT) variations. The proposed…”
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  8. 8

    Simultaneous Spike Processing for 3D NAND-Based Spiking Neural Networks by Jeon, Bosung, Song, Seunghwan, Kim, Jae-Joon, Choi, Woo Young

    Published in IEEE electron device letters (01-03-2024)
    “…Compute-in-Memory (CiM) with high bit density is crucial for implementing large-scale neural networks, and the CiM based on a three-dimensional (3D) NAND can…”
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  9. 9

    Improved Synapse Device With MLC and Conductance Linearity Using Quantized Conduction for Neuromorphic Systems by Lim, Seokjae, Sung, Changhyuck, Kim, Hyungjun, Kim, Taesu, Song, Jeonghwan, Kim, Jae-Joon, Hwang, Hyunsang

    Published in IEEE electron device letters (01-02-2018)
    “…In this letter, we demonstrate the conductive-bridging RAM (CBRAM) with excellent multi-level cell (MLC) and linear conductance characteristics for an…”
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  10. 10

    Highly stacked 3D organic integrated circuits with via-hole-less multilevel metal interconnects by Yoo, Hocheon, Park, Hongkeun, Yoo, Seunghyun, On, Sungmin, Seong, Hyejeong, Im, Sung Gap, Kim, Jae-Joon

    Published in Nature communications (03-06-2019)
    “…Multilevel metal interconnects are crucial for the development of large-scale organic integrated circuits. In particular, three-dimensional integrated circuits…”
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  11. 11

    Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning by Yin, Shihui, Kim, Yulhwa, Han, Xu, Barnaby, Hugh, Yu, Shimeng, Luo, Yandong, He, Wangxin, Sun, Xiaoyu, Kim, Jae-Joon, Seo, Jae-sun

    Published in IEEE MICRO (01-11-2019)
    “…Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density,…”
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  12. 12

    A Capacitive Computing-In-Memory Circuit with Low Input Loading SRAM Bitcell and Adjustable ADC Input Range by Kim, Eunhwan, Oh, Hyunmyung, Kang, Nameun, Park, Jihoon, Kim, Jae-Joon

    “…We present a 9T1C SRAM cell-based capacitive computing-in-memory circuit for neural network computation. The proposed design improves tolerance against process…”
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  13. 13

    GeCo: Classification Restricted Boltzmann Machine Hardware for On-Chip Semisupervised Learning and Bayesian Inference by Yi, Wooseok, Park, Junki, Kim, Jae-Joon

    “…The probabilistic Bayesian inference of real-time input data is becoming more popular, and the importance of semisupervised learning is growing. We present a…”
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  14. 14

    A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS by Ik Joon Chang, Jae-Joon Kim, Park, S.P., Roy, K.

    Published in IEEE journal of solid-state circuits (01-02-2009)
    “…Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications…”
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  15. 15

    Effect of Carrier Transport Process on Tunneling Electroresistance in Ferroelectric Tunnel Junction by Koo, Ryun-Han, Shin, Wonjun, Min, Kyung Kyu, Kwon, Dongseok, Kim, Dae Hwan, Kim, Jae-Joon, Kwon, Daewoong, Lee, Jong-Ho

    Published in IEEE electron device letters (01-01-2023)
    “…We demonstrate the factors that determine the tunneling electroresistance (TER) of the ferroelectric tunnel junction (FTJ) by investigating the effects of…”
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  16. 16

    Optimizing Post-Metal Annealing Temperature Considering Different Resistive Switching Mechanisms in Ferroelectric Tunnel Junction by Koo, Ryun-Han, Shin, Wonjun, Min, Kyung Kyu, Kwon, Dongseok, Kim, Jae-Joon, Kwon, Daewoong, Lee, Jong-Ho

    Published in IEEE electron device letters (01-06-2023)
    “…We investigate the effect of post-metal annealing temperature ( T PMA ) on ferroelectric (FE) resistive switching (RS) and non-FE RS in HfO x ferroelectric…”
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  17. 17

    Multi-Stage Organic Logic Circuits Using Via-Hole-Less Metal Interconnects by Park, Hongkeun, Yoo, Hocheon, Lee, Chungryeol, Kim, Jae-Joon, Im, Sung Gap

    Published in IEEE electron device letters (01-11-2020)
    “…Multi-metal interconnection is a crucial technology for the development of large-scale integrated circuits (ICs). However, organic semiconductors are not…”
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  18. 18

    Input Voltage Mapping Optimized for Resistive Memory-Based Deep Neural Network Hardware by Kim, Taesu, Kim, Hyungjun, Kim, Jinseok, Kim, Jae-Joon

    Published in IEEE electron device letters (01-09-2017)
    “…Artificial neural network (ANN) computations based on graphics processing units (GPUs) consume high power. Resistive random-access memory (RRAM) has been…”
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  19. 19

    Gate-tunable gas sensing behaviors in air-stable ambipolar organic thin-film transistors by Kwon, Hyunah, Yoo, Hocheon, Nakano, Masahiro, Takimiya, Kazuo, Kim, Jae-Joon, Kim, Jong Kyu

    Published in RSC advances (09-01-2020)
    “…Chemiresistive gas sensors, which exploit their electrical resistance in response to changes in nearby gas environments, usually achieve selective gas…”
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  20. 20

    Reliability Improvement in Vertical NAND Flash Cells Using Adaptive Incremental Step Pulse Programming (A-ISPP) and Incremental Step Pulse Erasing (ISPE) by Park, Sung-Ho, Yoo, Ho-Nam, Yang, Yeongheon, Kim, Jae-Joon, Lee, Jong-Ho

    Published in IEEE transactions on electron devices (01-03-2024)
    “…In order to improve the reliability of vertical NAND (V-NAND) flash memory cells, a scheme using adaptive incremental step pulse programming (A-ISPP) and…”
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