Search Results - "Kim, Jae‐Joon"
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Negative Transconductance Heterojunction Organic Transistors and their Application to Full‐Swing Ternary Circuits
Published in Advanced materials (Weinheim) (01-07-2019)“…Multivalued logic (MVL) computing could provide bit density beyond that of Boolean logic. Unlike conventional transistors, heterojunction transistors (H‐TRs)…”
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Mobileware: Distributed Architecture With Channel Stationary Dataflow for MobileNet Acceleration
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-09-2024)“…The depthwise separable convolution, a key feature of the MobileNet models, has a different input reuse pattern from the conventional standard convolution, and…”
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V-LSTM: An Efficient LSTM Accelerator using Fixed Nonzero-Ratio Viterbi-Based Pruning
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-10-2023)“…Long Short-Term Memory (LSTM) has been widely adopted in tasks with sequence data, such as speech recognition and language modeling. LSTM brought significant…”
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Efficient Convolutional Processing of Spiking Neural Network With Weight-Sharing Filters
Published in IEEE electron device letters (01-06-2023)“…The importance of implementing an efficient convolutional neural network (CNN) is increasing. A weight-sharing spiking CNN inference system (WS-SCNN) employing…”
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BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks
Published in IEEE journal of solid-state circuits (01-06-2022)“…We introduce an area/energy-efficient precision-scalable neural network accelerator architecture. Previous precision-scalable hardware accelerators have…”
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Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks
Published in IEEE transactions on very large scale integration (VLSI) systems (01-12-2023)“…Binary neural networks (BNNs) largely reduce the memory footprint and computational complexity, so they are gaining interests on various mobile applications…”
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Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations
Published in IEEE journal of solid-state circuits (01-07-2021)“…We introduce a new clocking approach for digital systems to achieve better resilience to process, voltage, and temperature (PVT) variations. The proposed…”
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Simultaneous Spike Processing for 3D NAND-Based Spiking Neural Networks
Published in IEEE electron device letters (01-03-2024)“…Compute-in-Memory (CiM) with high bit density is crucial for implementing large-scale neural networks, and the CiM based on a three-dimensional (3D) NAND can…”
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Improved Synapse Device With MLC and Conductance Linearity Using Quantized Conduction for Neuromorphic Systems
Published in IEEE electron device letters (01-02-2018)“…In this letter, we demonstrate the conductive-bridging RAM (CBRAM) with excellent multi-level cell (MLC) and linear conductance characteristics for an…”
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Highly stacked 3D organic integrated circuits with via-hole-less multilevel metal interconnects
Published in Nature communications (03-06-2019)“…Multilevel metal interconnects are crucial for the development of large-scale organic integrated circuits. In particular, three-dimensional integrated circuits…”
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Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning
Published in IEEE MICRO (01-11-2019)“…Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density,…”
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A Capacitive Computing-In-Memory Circuit with Low Input Loading SRAM Bitcell and Adjustable ADC Input Range
Published in IEEE transactions on circuits and systems. II, Express briefs (01-09-2023)“…We present a 9T1C SRAM cell-based capacitive computing-in-memory circuit for neural network computation. The proposed design improves tolerance against process…”
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GeCo: Classification Restricted Boltzmann Machine Hardware for On-Chip Semisupervised Learning and Bayesian Inference
Published in IEEE transaction on neural networks and learning systems (01-01-2020)“…The probabilistic Bayesian inference of real-time input data is becoming more popular, and the importance of semisupervised learning is growing. We present a…”
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A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS
Published in IEEE journal of solid-state circuits (01-02-2009)“…Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications…”
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Effect of Carrier Transport Process on Tunneling Electroresistance in Ferroelectric Tunnel Junction
Published in IEEE electron device letters (01-01-2023)“…We demonstrate the factors that determine the tunneling electroresistance (TER) of the ferroelectric tunnel junction (FTJ) by investigating the effects of…”
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Optimizing Post-Metal Annealing Temperature Considering Different Resistive Switching Mechanisms in Ferroelectric Tunnel Junction
Published in IEEE electron device letters (01-06-2023)“…We investigate the effect of post-metal annealing temperature ( T PMA ) on ferroelectric (FE) resistive switching (RS) and non-FE RS in HfO x ferroelectric…”
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Multi-Stage Organic Logic Circuits Using Via-Hole-Less Metal Interconnects
Published in IEEE electron device letters (01-11-2020)“…Multi-metal interconnection is a crucial technology for the development of large-scale integrated circuits (ICs). However, organic semiconductors are not…”
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Input Voltage Mapping Optimized for Resistive Memory-Based Deep Neural Network Hardware
Published in IEEE electron device letters (01-09-2017)“…Artificial neural network (ANN) computations based on graphics processing units (GPUs) consume high power. Resistive random-access memory (RRAM) has been…”
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Gate-tunable gas sensing behaviors in air-stable ambipolar organic thin-film transistors
Published in RSC advances (09-01-2020)“…Chemiresistive gas sensors, which exploit their electrical resistance in response to changes in nearby gas environments, usually achieve selective gas…”
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Reliability Improvement in Vertical NAND Flash Cells Using Adaptive Incremental Step Pulse Programming (A-ISPP) and Incremental Step Pulse Erasing (ISPE)
Published in IEEE transactions on electron devices (01-03-2024)“…In order to improve the reliability of vertical NAND (V-NAND) flash memory cells, a scheme using adaptive incremental step pulse programming (A-ISPP) and…”
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