Search Results - "Kikuchi, Katsuya"

Thermal management of a 3D packaging structure for superconducting quantum annealing machines by Feng, Wei, Kikuchi, Katsuya, Hidaka, Mutsuo, Yamamori, Hirotake, Araga, Yuuki, Makise, Kazumasa, Kawabata, Shiro

“…Quantum annealing (QA) is a computing paradigm for solving combinatorial optimization problems by finding the low-energy configurations of complicated Ising…”
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Demonstration of 90 000 superconductive bump connections for massive quantum computing by Araga, Yuuki, Nakagawa, Hiroshi, Hashino, Masaru, Kikuchi, Katsuya

“…Abstract We developed fabrication and bonding technology of superconductive bump for massive quantum computing. A bonded test vehicle demonstrates supercurrent…”
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Toward Practical-Scale Quantum Annealing Machine for Prime Factoring by Maezawa, Masaaki, Fujii, Go, Hidaka, Mutsuo, Imafuku, Kentaro, Kikuchi, Katsuya, Koike, Hanpei, Makise, Kazumasa, Nagasawa, Shuichi, Nakagawa, Hiroshi, Ukibe, Masahiro, Kawabata, Shiro

“…We propose a prime factorizer operated in a framework of quantum annealing (QA). The idea is the inverse operation of a multiplier implemented with QA-based…”
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Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices by Miki, Takuji, Nagata, Makoto, Sonoda, Hiroki, Miura, Noriyuki, Okidono, Takaaki, Araga, Yuuki, Watanabe, Naoya, Shimamoto, Haruo, Kikuchi, Katsuya

“…This article presents a cryptographic key protection technique from physical security attacks through Si-backside of IC chip. Flip-chip packaging leads to a…”
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Residual stress investigation of via-last through-silicon via by polarized Raman spectroscopy measurement and finite element simulation by Feng, Wei, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya

“…The residual stresses induced around through-silicon vias (TSVs) by a fabrication process is one of the major concerns of reliability. We proposed a…”
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Evaluation of substrate noise suppression method to mitigate crosstalk among trough-silicon vias by Araga, Yuuki, Kikuchi, Katsuya, Aoyagi, Masahiro

“…Substrate noise from a single through-silicon via (TSV) and the noise attenuation by a substrate tap and a guard ring are clarified. A CMOS test vehicle is…”
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Validation of TSV thermo-mechanical simulation by stress measurement by Feng, Wei, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya

“…Because of the large mismatch in coefficients of thermal expansion (CTE) between copper vias and the silicon substrate in through-silicon vias (TSVs), thermal…”
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Fabrication and stress analysis of annular-trench-isolated TSV by Feng, Wei, Bui, Tung Thanh, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya

“…The large mismatches among the coefficients of thermal expansion (CTE) of the metal via, insulator liner, and Si substrate of the through-silicon via (TSV)…”
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Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer by Watanabe, Naoya, Kikuchi, Hidekazu, Yanagisawa, Azusa, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Nakamura, Akio

“…We combined a "via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer" with the solder bonding…”
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Quaternary and secondary structural imaging of a human hair by a VSFG-detected IR super-resolution microscope by Sakai, Makoto, Kikuchi, Katsuya, Fujii, Masaaki

“…[Display omitted] ► IR super-resolution image of cross section of a human black hair were measured. ► For the amide III band, human hair gave strong VSFG…”
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Investigation of transient thermal dissipation in thinned LSI for advanced packaging by Araga, Yuuki, Shimamoto, Haruo, Melamed, Samson, Kikuchi, Katsuya, Aoyagi, Masahiro

“…Thinning of LSI is necessary for superior form factor and performance in dense cutting-edge packaging technologies. At the same time, degradation of thermal…”
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Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer by Watanabe, Naoya, Kikuchi, Hidekazu, Yanagisawa, Azusa, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Nakamura, Akio

“…A high-yield via-last through silicon via (TSV) process has been developed using notchless Si etching and wet cleaning of the first metal layer. In this…”
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Measurement and Analysis of Power Noise Characteristics for EMI Awareness of Power Delivery Networks in 3-D Through-Silicon Via Integration by Araga, Yuuki, Nagata, Makoto, Miura, Noriyuki, Ikeda, Hiroaki, Kikuchi, Katsuya

“…The 3-D-stacked large-scale integration (3-D-LSI) chips provide densely integrated capacitance and low impedance in vertically and horizontally distributed…”
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Cool Interconnect: A 1024-bit Wide Bus for Chip-to-Chip Communications in 3-D Integrated Circuits by Melamed, Samson, Imura, Fumito, Nakagawa, Hiroshi, Kikuchi, Katsuya, Hagimoto, Michiya, Matsumoto, Yukoh, Aoyagi, Masahiro

“…In this paper, we present "Cool Interconnect," a 1024-bit wide bus that we have developed to provide a standardized method of interconnecting chips in 3-D…”
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Hardness Characteristics of Au Cone-Shaped Bumps Targeted for 3-D Packaging Applications by Lim, Ying Ying, Nakagawa, Hiroshi, Hashino, Masaru, Aoyagi, Masahiro, Kikuchi, Katsuya

“…Three-dimensional large scale integration (3D-LSI) packaging is crucial toward obtaining increased circuit density within a small footprint. In a 3D-LSI…”
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Fine Cone-shaped Bumps for Three-dimensional LSI Package—An Optimization of Thermocompression Bonding Process by Nemoto, Shunsuke, Lim, Ying Ying, Nakagawa, Hiroshi, Kikuchi, Katsuya, Aoyagi, Masahiro

“…Fine cone-shaped bumps (6 ?m) were fabricated by a nanoparticle deposition method, where the nanoparticles were deposited onto hole patterns defined in a…”
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A method enabling height-control of chips for edge-emitting laser stacking by Tung, Bui Thanh, Ma, Laina, Amano, Takeru, Kikuchi, Katsuya, Mori, Masahiko, Aoyagi, Masahiro

“…In this paper we present a stacking method that enables the mounting of edge-emitting laser (EEL) devices at compulsory positions for feeding a coupling…”
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EMI performance of power delivery networks in 3D TSV integration by Araga, Yuuki, Nagata, Makoto, Miura, Noriyuki, Ikeda, Hiroaki, Kikuchi, Katsuya

“…A three-dimensionally stacked, large-scale integration (3D-LSI) chip naturally provides densely capacitive and low-impedance characteristics in vertically and…”
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15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications by Tung, Bui Thanh, Kato, Fumiki, Watanabe, Naoya, Nemoto, Shunsuke, Kikuchi, Katsuya, Aoyagi, Masahiro

“…In this paper, we report the development of reliable fine-pitch micro bump interconnections that used a high-precision room-temperature bonding approach. The…”
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Heat transfer study of 3D packaging structure with superconducting TSV for practical-scale quantum annealing machines by Feng, Wei, Kikuchi, Katsuya

“…Abstract To avoid the interconnect crowding in a planar structure, three-dimensional (3D) integrated technologies are necessary for realizing practical…”
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