Search Results - "Kikuchi, Hidekazu"

Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer by Watanabe, Naoya, Kikuchi, Hidekazu, Yanagisawa, Azusa, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Nakamura, Akio

“…We combined a "via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer" with the solder bonding…”
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Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer by Watanabe, Naoya, Kikuchi, Hidekazu, Yanagisawa, Azusa, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Nakamura, Akio

“…A high-yield via-last through silicon via (TSV) process has been developed using notchless Si etching and wet cleaning of the first metal layer. In this…”
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Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack by Matsumoto, Keiji, Ibaraki, Soichiro, Sueoka, Kuniaki, Sakuma, Katsuyuki, Kikuchi, Hidekazu, Orii, Yasumitsu, Yamada, Fumiaki

“…To propose an appropriate cooling solution for a three-dimensional (3D) chip stack at the design phase, it is necessary to estimate the total thermal…”
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Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements by Matsumoto, K., Ibaraki, S., Sueoka, K., Sakuma, K., Kikuchi, H., Orii, Y., Yamada, F.

“…For the thermal management of three-dimensional (3D) chip stack, its thermal resistance needs to be clearly understood. In this study, 3D stacked test chips…”
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A 6.9- \mu m Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC by Sakakibara, Masaki, Ogawa, Koji, Sakai, Shin, Tochigi, Yasuhisa, Honda, Katsumi, Kikuchi, Hidekazu, Wada, Takuya, Kamikubo, Yasunobu, Miura, Tsukasa, Nakamizo, Masahiko, Jyo, Naoki, Hayashibara, Ryo, Miyata, Shinya, Yamamoto, Satoshi, Ota, Yoshiyuki, Takahashi, Hirotsugu, Taura, Tadayuki, Oike, Yusuke, Tatani, Keiji, Ezaki, Takayuki, Hirayama, Teruo

“…In this paper, we report on a back-illuminated, global shutter, CMOS image sensor (CIS) with a pixel-parallel, single-slope analog-to-digital converter (ADC)…”
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Additive value of the right parasternal view for the assessment of aortic stenosis by Shimamura, Toshio, Izumo, Masaki, Sato, Yukio, Shiokawa, Noriko, Uenomachi, Nina, Miyauchi, Motoki, Miyamoto, Junko, Kikuchi, Hidekazu, Shinoda, Junko, Okamura, Takanori, Akashi, Yoshihiro J.

“…Background Although Doppler evaluation using a multiplanar method is recommended to assess the severity of aortic stenosis (AS) with transthoracic…”
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A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC by Sakakibara, Masaki, Ogawa, Koji, Sakai, Shin, Tochigi, Yasuhisa, Honda, Katsumi, Kikuchi, Hidekazu, Wada, Takuya, Kamikubo, Yasunobu, Miura, Tsukasa, Nakamizo, Masahiko, Jyo, Naoki, Hayashibara, Ryo, Furukawa, Yohei, Miyata, Shinya, Yamamoto, Satoshi, Ota, Yoshiyuki, Takahashi, Hirotsugu, Taura, Tadayuki, Oike, Yusuke, Tatani, Keiji, Nagano, Takashi, Ezaki, Takayuki, Hirayama, Teruo

“…Rolling-shutter CMOS image sensors (CISs) are widely used [1,2]. However, the distortion of moving subjects remains an unresolved problem, regardless of the…”
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A 6.9-[Formula Omitted]m Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC by Sakakibara, Masaki, Ogawa, Koji, Sakai, Shin, Tochigi, Yasuhisa, Honda, Katsumi, Kikuchi, Hidekazu, Wada, Takuya, Kamikubo, Yasunobu, Miura, Tsukasa, Nakamizo, Masahiko, Jyo, Naoki, Hayashibara, Ryo, Miyata, Shinya, Yamamoto, Satoshi, Ota, Yoshiyuki, Takahashi, Hirotsugu, Taura, Tadayuki, Oike, Yusuke, Tatani, Keiji, Ezaki, Takayuki, Hirayama, Teruo

“…In this paper, we report on a back-illuminated, global shutter, CMOS image sensor (CIS) with a pixel-parallel, single-slope analog-to-digital converter (ADC)…”
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A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology by Kurita, Y., Matsui, S., Takahashi, N., Soejima, K., Komuro, M., Itou, M., Kakegawa, C., Kawano, M., Egawa, Y., Saeki, Y., Kikuchi, H., Kato, O., Yanagisawa, A., Mitsuhashi, T., Ishino, M., Shibata, K., Uchiyama, S., Yamada, J., Ikeda, H.

“…A general-purpose 3D-LSI platform technology for a high-capacity stacked memory integrated on a logic device was developed for high-performance,…”
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Thermal design guidelines for a three-dimensional (3D) chip stack, including cooling solutions by Matsumoto, Keiji, Ibaraki, Soichiro, Sueoka, Kuniaki, Sakuma, Katsuyuki, Kikuchi, Hidekazu, Orii, Yasumitsu, Yamada, Fumiaki, Fujihara, Kohei, Takamatsu, Junichi, Kondo, Koji

“…The thermal resistance of a three-dimensional (3D) chip stack is evaluated, based on the measured thermal resistances of 3D stacked thermal test chips which…”
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Wet cleaning process for high-yield via-last TSV formation by Watanabe, Naoya, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Kikuchi, Hidekazu, Yanagisawa, Azusa, Nakamura, Akio

“…The backside via-last through silicon via (TSV) process is a simple and cost-effective approach for three-dimensional integration. However, it has two…”
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Metal Contamination Evaluation of Via-Last Cu TSV Process Using Notchless Si Etching and Wet Cleaning of the First Metal Layer by Watanabe, Naoya, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Kikuchi, Hidekazu, Yanagisawa, Azusa, Nakamura, Akio

“…To confirm the effectiveness of the via-last through silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer, we…”
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A 1-bit serial transceiver chip set for full-color XGA pictures by Kikuchi, Hidekazu, Suzuki, Norihito, IIzuka, Hiroshi, Takesita, Tohru

“…A 1‐bit serial transceiver chip set for the full‐color moving picture was developed. It introduced a new data coding for the serial transmission and novel…”
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Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack by Matsumoto, Keiji, Ibaraki, Soichiro, Sueoka, Kuniaki, Sakuma, Katsuyuki, Kikuchi, Hidekazu, Mori, Hiroyuki, Orii, Yasumitsu, Yamada, Fumiaki, Fujihara, Kohei, Takamatsu, Junichi, Kondo, Koji

“…In ASET (Association of Super Advanced Electronics Technologies), the thermal resistances of three-dimensional (3D) chip stacks have been measured by using 3D…”
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TSV diagnostics by X-ray microscopy by Sueoka, K., Yamada, F., Horibe, A., Kikuchi, H., Minami, K., Orii, Y.

“…TSV (Through Silicon Via) is one of the key elements for building 3D integrated silicon devices with high bandwidth interconnections. In this paper, we propose…”
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Gigabit Video Interface: A Fully Serialized Data Transmission System For Digital Moving Pictures by Kikuchi, Fukuzaki, Tamaki, Takeshita

“…A I -bit serial 1.56Gb/s data transceiver chip set for base band transmission of XGA moving pictures was developed. It integrates PLLs, ENC/ DEC, cable…”
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Three-dimensional integration scheme using hybrid wafer bonding and via-last TSV process by Takeda, K., Aoki, M., Hozawa, K., Furuta, F., Yanagisawa, A., Kikuchi, H., Mitsuhashi, T., Kobayashi, H.

“…A wafer-level three-dimensional (3D) integration scheme for forming via-last through-silicon vias (TSVs) was developed. This scheme includes wafer-to-wafer…”
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Thermal resistance evaluation of a three-dimensional (3D) chip stack by Matsumoto, K, Ibaraki, S, Sakuma, K, Sueoka, K, Kikuchi, H, Orii, Y, Yamada, F

“…Three-dimensional (3D) chip stacks are receiving more attention for system performance enhancements, due to their higher interconnect density and shorter…”
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High density 3D integration by pre-applied Inter Chip Fill by Horibe, A, Sueoka, K, Sakuma, K, Kohara, S, Matsumoto, K, Kikuchi, H, Orii, Y, Mitsuhashi, T, Yamada, F

“…28,561 bumps/die were electrically connected by Stack Joining method using pre-applied Inter Chip Fill resin…”
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