Search Results - "Kibune, M"

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS by Kanda, K., Tamura, H., Yamamoto, T., Matsubara, S., Kibune, M., Doi, Y., Shibasaki, T., Tzartzanis, N., Kristensson, A., Parikh, S., Ide, S., Tsunoda, Y., Yamabana, T., Sugawara, M., Kuwata, N., Ikeuchi, T., Ogawa, J., Walker, W.W.

“…This paper presents a 40 Gb/s serializer IC in 65 nm bulk CMOS technology. The IC has an SFI5.2-compliant 10 Gb/s input interface and supports two different…”
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A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization by Higashi, H., Masaki, S., Kibune, M., Matsubara, S., Chiba, T., Doi, Y., Yamaguchi, H., Takauchi, H., Ishida, H., Gotoh, K., Tamura, H.

“…A 5-6.4 Gb/s transceiver, consisting of a parallel 12-channel transmitter (Tx), 12-channel receiver (Rx), clock generators based on LC-VCO phase-locked loops…”
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A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique by Okaniwa, Y., Tamura, H., Kibune, M., Yamazaki, D., Tsz-Shing Cheung, Ogawa, J., Tzartzanis, N., Walker, W.W., Kuroda, T.

“…A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-/spl mu/m standard…”
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A CMOS multichannel 10-Gb/s transceiver by Takauchi, H., Tamura, H., Matsubara, S., Kibune, M., Doi, Y., Chiba, T., Anbutsu, H., Yamaguchi, H., Mori, T., Takatsu, M., Gotoh, K., Sakai, T., Yamamura, T.

“…We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two…”
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Spin-charge separation in single-chain compound Sr2CuO3 studied by angle-resolved photoemission by FUJISAWA, H, YOKOYA, T, TAKAHASHI, T, MIYASAKA, S, KIBUNE, M, TAKAGI, H

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5Gb/s bidirectional balanced-line link compliant with plesiochronous clocking by Tamura, H, Kibune, M, Takahashi, Y, Doi, Y, Chiba, T, Higashi, H, Takauchi, H, Ishida, H, Gotoh, K

“…A 5Gb/s bidirectional link carrying 2.5Gb/s non-return-to-zero (NRZ) signals on balanced line was discussed. The transmitter (Tx) section of this link…”
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Influence of adsorption behaviour of a silane coupling agent on interlaminar fracture in glass fibre fabric-reinforced unsaturated polyester laminates by SUZUKI, Y, MAEKAWA, Z, HAMADA, H, KIBUNE, M, HOJO, M, IKUTA, N

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A CMOS multi-channel 10Gb/s transceiver by Takauchi, H., Tamura, H., Matsubara, S., Kibune, M., Doi, Y., Chiba, T., Anbutsu, H., Yamaguchi, H., Mori, T., Takatsu, M., Gotoh, K., Sakai, T., Yamamura, T.

“…A quad 10Gb/s transceiver in 0.11/spl mu/m CMOS communicates electric signals over balanced copper media. The transceiver uses a single 1.2V power supply and…”
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An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS by Abiri, B., Sheikholeslami, A., Tamura, H., Kibune, M.

“…This paper proposes an adaptation engine for a 2 blind sampling ADC-based receiver. The proposed adaptive engine uses a triangular desired waveform, instead of…”
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A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS by Abiri, B, Shivnaraine, R, Sheikholeslami, A, Tamura, H, Kibune, M

“…Burst-mode clock and data recovery circuits (BMCDR) are widely used in passive optical networks (PON) [1] and as a replacement for conventional CDRs in…”
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A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS by Nedovic, N, Kristensson, A, Parikh, S, Reddy, S, McLeod, S, Tzartzanis, N, Kanda, K, Yamamoto, T, Matsubara, S, Kibune, M, Doi, Y, Ide, S, Tsunoda, Y, Yamabana, T, Shibasaki, T, Tomita, Y, Hamada, T, Sugawara, M, Ikeuchi, T, Kuwata, N, Tamura, H, Ogawa, J, Walker, W

“…A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical…”
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A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS by TOMITA, Yasumoto, KIBUNE, Masaya, OGAWA, Junji, WALKER, William W, TAMURA, Hirotaka, KURODA, Tadahiro

“…A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The…”
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Split capacitor DAC mismatch calibration in successive approximation ADC by Yanfei Chen, Xiaolei Zhu, Tamura, H., Kibune, M., Tomita, Y., Hamada, T., Yoshioka, M., Ishikawa, K., Takayama, T., Ogawa, J., Tsukamoto, S., Kuroda, T.

“…A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for…”
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A blind baud-rate ADC-based CDR by Ting, C., Liang, J., Sheikholeslami, A., Kibune, M., Tamura, H.

“…ADC-based receivers process the received data in the digital domain, eliminating the need for much of the analog front end. In addition, a feed-forward blind…”
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A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS by Abiri, B, Sheikholeslami, A, Tamura, H, Kibune, M

“…ADC-based receivers allow for extensive equalization in the digital domain and therefore can easily compensate for channel loss at higher data rates. Digital…”
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A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-[Formula Omitted] CMOS by Tomita, Y, Tamura, H, Kibune, M, Ogawa, J, Gotoh, K, Kuroda, T

“…This paper presents a 20-Gb/s simultaneous bidirectional transceiver using a resistor-transconductor (R-gm) hybrid in standard 0.11-mum CMOS. The R-gm hybrid…”
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5-6.4 Gbps 12 channel transceiver with pre-emphasis and equalizer by Higashi, H., Masaki, S., Kibune, M., Matsubara, S., Chiba, T., Doi, Y., Yamaguchi, H., Takauchi, H., Ishida, H., Gotoh, K., Tamura, H.

“…A 5 Gbps to 6.4 Gbps transceiver consists of a parallel 12-channel transmitter (Tx), 12-channel receiver (Rx), clock generators based on LC-VCO PLLs, and a…”
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A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11- \mu} CMOS by Tomita, Y., Tamura, H., Kibune, M., Ogawa, J., Gotoh, K., Kuroda, T.

“…This paper presents a 20-Gb/s simultaneous bidirectional transceiver using a resistor-transconductor (R-gm) hybrid in standard 0.11-mum CMOS. The R-gm hybrid…”
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A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-mum CMOS by Tomita, Y, Kibune, M, Ogawa, J, Walker, W W, Tamura, H, Kuroda, T

“…A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The…”
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A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-[micro]m CMOS by Tomita, Y, Kibune, M, Ogawa, J, Walker, W.W, Tamura, H, Kuroda, T

“…The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input…”
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