Search Results - "Ketkar, Mahesh"

Refine Results
  1. 1

    Mining Patterns From Concurrent Execution Traces by Ahmed, Md Rubel, Zheng, Hao, Mukherjee, Parijat, Ketkar, Mahesh C., Yang, Jin

    “…This article proposes a specification mining framework, FlowMiner , that automatically mines patterns from highly concurrent communication traces for…”
    Get full text
    Journal Article
  2. 2

    Model Synthesis for Communication Traces of System Designs by Zheng, Hao, Ahmed, Md Rubel, Mukherjee, Parijat, Ketkar, Mahesh C., Yang, Jin

    “…Concise and abstract models of system-level behaviors are invaluable in design analysis, testing, and validation. In this paper, we consider the problem of…”
    Get full text
    Conference Proceeding
  3. 3

    Mining Message Flows from System-on-Chip Execution Traces by Ahmed, Md Rubel, Zheng, Hao, Mukherjee, Parijat, Ketkar, Mahesh C., Yang, Jin

    “…Comprehensive and well-defined specifications are necessary to perform rigorous and thorough validation of system-on-chip (SoC) designs. Message flows specify…”
    Get full text
    Conference Proceeding
  4. 4

    A Comparative Study of Specification Mining Methods for SoC Communication Traces by Ahmed, Md Rubel, Zheng, Hao, Mukherjee, Parijat, Ketkar, Mahesh C., Yang, Jin

    “…This paper aims to study how existing trace mining methods work, and their strengths and weaknesses in the context of communication-centric system-on-chip…”
    Get full text
    Conference Proceeding
  5. 5

    End-to-End Cloud Application Cloning With Ditto by Liang, HMingyu, Gan, Yu, Li, Yueying, Torres, Carlos, Dhanotia, Abhishek, Ketkar, Mahesh, Delimitrou, Christina

    Published in IEEE MICRO (01-07-2024)
    “…The lack of publicly available cloud services has been a recurring problem in architecture and systems. Although open source benchmarks exist, they do not…”
    Get full text
    Journal Article
  6. 6

    Standby power optimization via transistor sizing and dual threshold voltage assignment by Ketkar, Mahesh, Sapatnekar, Sachin S.

    “…This paper presents a novel enumerative approach, with provable and efficient pruning techniques, for dual threshold voltage (Vt) assignment at the transistor…”
    Get full text
    Conference Proceeding
  7. 7

    Automatic Microprocessor Performance Bug Detection by Barboza, Erick Carvajal, Jacob, Sara, Ketkar, Mahesh, Kishinevsky, Michael, Gratz, Paul, Hu, Jiang

    “…Processor design validation and debug is a difficult and complex task, which consumes the lion's share of the design process. Design bugs that affect processor…”
    Get full text
    Conference Proceeding
  8. 8

    Aiding Microprocessor Performance Validation with Machine Learning by Barboza, Erick Carvajal, Ketkar, Mahesh, Gratz, Paul, Hu, Jiang

    “…Microprocessor validation is a complex task that consumes substantial engineering time. Degradation of the system performance that does not affect its…”
    Get full text
    Conference Proceeding
  9. 9

    Gate Sizing for Cell-Library-Based Designs by Shiyan Hu, Ketkar, M., Jiang Hu

    “…With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies…”
    Get full text
    Journal Article
  10. 10

    A microarchitecture-based framework for pre- and post-silicon power delivery analysis by Ketkar, Mahesh, Chiprout, Eli

    “…Variations in power supply voltage, which is a function of the power delivery network and dynamic current consumption, can affect circuit reliability. Much…”
    Get full text
    Conference Proceeding
  11. 11

    Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs by Cao, Yuting, Mukherjee, Parijat, Ketkar, Mahesh, Yang, Jin, Zheng, Hao

    “…Comprehensive specifications are essential for various activities across the entire validation continuum for system-on-chip (SoC) designs. However,…”
    Get full text
    Conference Proceeding
  12. 12

    Machine Learning for Microprocessor Performance Bug Localization by Barboza, Erick Carvajal, Ketkar, Mahesh, Kishinevsky, Michael, Gratz, Paul, Hu, Jiang

    Published 27-03-2023
    “…The validation process for microprocessors is a very complex task that consumes substantial engineering time during the design process. Bugs that degrade…”
    Get full text
    Journal Article
  13. 13

    End-to-End Application Cloning for Distributed Cloud Microservices with Ditto by Liang, Mingyu, Gan, Yu, Li, Yueying, Torres, Carlos, Danotia, Abhishek, Ketkar, Mahesh, Delimitrou, Christina

    Published 28-12-2022
    “…We present Ditto, an automated framework for cloning end-to-end cloud applications, both monolithic and microservices, which captures I/O and network activity,…”
    Get full text
    Journal Article
  14. 14

    Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs by Cao, Yuting, Mukherjee, Parijat, Ketkar, Mahesh, Yang, Jin, Zheng, Hao

    Published 29-04-2020
    “…Comprehensive specifications are essential for various activities across the entire validation continuum for system-on-chip (SoC) designs. However,…”
    Get full text
    Journal Article
  15. 15

    MQL: ML-Assisted Queuing Latency Analysis for Data Center Networks by Narayana, Shruti Yadav, Tong, Jie, Krishnakumar, Anish, Yildirim, Nuriye, Shriver, Emily, Ketkar, Mahesh, Ogras, Umit Y.

    “…Data center network (DCN) performance analysis is becoming increasingly critical due to the growing data center scale and proliferation of latency-critical…”
    Get full text
    Conference Proceeding
  16. 16

    A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates] by Kasamsetty, K., Ketkar, M., Sapatnekar, S.S.

    “…This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model…”
    Get full text
    Journal Article
  17. 17

    Model Synthesis for Communication Traces of System-on-Chip Designs by Zheng, Hao, Ahmed, Md Rubel, Mukherjee, Parijat, Ketkar, Mahesh C, Yang, Jin

    Published 13-02-2021
    “…Concise and abstract models of system-level behaviors are invaluable in design analysis, testing, and validation. In this paper, we consider the problem of…”
    Get full text
    Journal Article
  18. 18

    Automatic Microprocessor Performance Bug Detection by Barboza, Erick Carvajal, Jacob, Sara, Ketkar, Mahesh, Kishinevsky, Michael, Gratz, Paul, Hu, Jiang

    Published 17-11-2020
    “…Processor design validation and debug is a difficult and complex task, which consumes the lion's share of the design process. Design bugs that affect processor…”
    Get full text
    Journal Article
  19. 19

    Mining Message Flows from System-on-Chip Execution Traces by Ahmed, MD Rubel, Zheng, Hao, Mukherjee, Parijat, Ketkar, Mahesh C, Yang, Jin

    Published 22-05-2020
    “…Comprehensive and well-defined specifications are necessary to perform rigorous and thorough validation of system-on-chip (SoC) designs. Message flows specify…”
    Get full text
    Journal Article
  20. 20

    PerfProbe: A Systematic, Cross-Layer Performance Diagnosis Framework for Mobile Platforms by Hong, David Ke, Nikravesh, Ashkan, Mao, Z. Morley, Ketkar, Mahesh, Kishinevsky, Michael

    “…User-perceived performance slowdown in mobile apps can occur in unpredictable and sophisticated ways, with root cause spanning at different layers (app or…”
    Get full text
    Conference Proceeding