Search Results - "Ketkar, Mahesh"
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1
Mining Patterns From Concurrent Execution Traces
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-08-2022)“…This article proposes a specification mining framework, FlowMiner , that automatically mines patterns from highly concurrent communication traces for…”
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2
Model Synthesis for Communication Traces of System Designs
Published in 2021 IEEE 39th International Conference on Computer Design (ICCD) (01-10-2021)“…Concise and abstract models of system-level behaviors are invaluable in design analysis, testing, and validation. In this paper, we consider the problem of…”
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Conference Proceeding -
3
Mining Message Flows from System-on-Chip Execution Traces
Published in 2021 22nd International Symposium on Quality Electronic Design (ISQED) (07-04-2021)“…Comprehensive and well-defined specifications are necessary to perform rigorous and thorough validation of system-on-chip (SoC) designs. Message flows specify…”
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4
A Comparative Study of Specification Mining Methods for SoC Communication Traces
Published in 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (01-07-2021)“…This paper aims to study how existing trace mining methods work, and their strengths and weaknesses in the context of communication-centric system-on-chip…”
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5
End-to-End Cloud Application Cloning With Ditto
Published in IEEE MICRO (01-07-2024)“…The lack of publicly available cloud services has been a recurring problem in architecture and systems. Although open source benchmarks exist, they do not…”
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6
Standby power optimization via transistor sizing and dual threshold voltage assignment
Published in Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design (10-11-2002)“…This paper presents a novel enumerative approach, with provable and efficient pruning techniques, for dual threshold voltage (Vt) assignment at the transistor…”
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7
Automatic Microprocessor Performance Bug Detection
Published in 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA) (01-02-2021)“…Processor design validation and debug is a difficult and complex task, which consumes the lion's share of the design process. Design bugs that affect processor…”
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Conference Proceeding -
8
Aiding Microprocessor Performance Validation with Machine Learning
Published in 2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (05-05-2024)“…Microprocessor validation is a complex task that consumes substantial engineering time. Degradation of the system performance that does not affect its…”
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9
Gate Sizing for Cell-Library-Based Designs
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-06-2009)“…With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies…”
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10
A microarchitecture-based framework for pre- and post-silicon power delivery analysis
Published in 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (12-12-2009)“…Variations in power supply voltage, which is a function of the power delivery network and dynamic current consumption, can affect circuit reliability. Much…”
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11
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs
Published in 2020 21st International Symposium on Quality Electronic Design (ISQED) (01-03-2020)“…Comprehensive specifications are essential for various activities across the entire validation continuum for system-on-chip (SoC) designs. However,…”
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Conference Proceeding -
12
Machine Learning for Microprocessor Performance Bug Localization
Published 27-03-2023“…The validation process for microprocessors is a very complex task that consumes substantial engineering time during the design process. Bugs that degrade…”
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13
End-to-End Application Cloning for Distributed Cloud Microservices with Ditto
Published 28-12-2022“…We present Ditto, an automated framework for cloning end-to-end cloud applications, both monolithic and microservices, which captures I/O and network activity,…”
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14
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs
Published 29-04-2020“…Comprehensive specifications are essential for various activities across the entire validation continuum for system-on-chip (SoC) designs. However,…”
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Journal Article -
15
MQL: ML-Assisted Queuing Latency Analysis for Data Center Networks
Published in 2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (01-04-2023)“…Data center network (DCN) performance analysis is becoming increasingly critical due to the growing data center scale and proliferation of latency-critical…”
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16
A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-07-2000)“…This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model…”
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Journal Article -
17
Model Synthesis for Communication Traces of System-on-Chip Designs
Published 13-02-2021“…Concise and abstract models of system-level behaviors are invaluable in design analysis, testing, and validation. In this paper, we consider the problem of…”
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Journal Article -
18
Automatic Microprocessor Performance Bug Detection
Published 17-11-2020“…Processor design validation and debug is a difficult and complex task, which consumes the lion's share of the design process. Design bugs that affect processor…”
Get full text
Journal Article -
19
Mining Message Flows from System-on-Chip Execution Traces
Published 22-05-2020“…Comprehensive and well-defined specifications are necessary to perform rigorous and thorough validation of system-on-chip (SoC) designs. Message flows specify…”
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Journal Article -
20
PerfProbe: A Systematic, Cross-Layer Performance Diagnosis Framework for Mobile Platforms
Published in 2019 IEEE/ACM 6th International Conference on Mobile Software Engineering and Systems (MOBILESoft) (01-05-2019)“…User-perceived performance slowdown in mobile apps can occur in unpredictable and sophisticated ways, with root cause spanning at different layers (app or…”
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Conference Proceeding