Search Results - "Keser, Beth"

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  1. 1

    The Redistributed Chip Package: A Breakthrough for Advanced Packaging by Keser, B., Amrine, C., Trung Duong, Fay, O., Hayes, S., Leal, G., Lytle, W., Mitchell, D., Wenzel, R.

    “…The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current…”
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    Conference Proceeding
  2. 2

    Flip-Chip Chip Scale Package (FCCSP) Process Characterization and Reliability of Coreless Thin Package with 7nm Si Technology by De Mesa, Eduardo, Wagner, Thomas, Keser, Beth, Proschwitz, Jan, Waidhas, Bernd

    “…Advanced silicon nodes are continuously pushing the cutting edge of assembly technology with coreless thin packages used in mobile and electronic products to…”
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    Conference Proceeding
  3. 3

    Foreword by Keser, Beth, Braunisch, Henning

    “…On behalf of the Program Committee and Executive Committee, it is our pleasure to welcome you to the 65th Electronic Components and Technology Conference…”
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    Conference Proceeding
  4. 4

    Study of the Board Level Reliability Performance of a Large 0.3 mm Pitch Wafer Level Package by Waidhas, Bernd, Proschwitz, Jan, Pietryga, Christoph, Wagner, Thomas, Keser, Beth

    “…Board level reliability investigations have been performed on 36 mm² wafer level packages (WLP) with a 0.3 mm ball pitch. Three different solder ball alloys…”
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    Conference Proceeding
  5. 5

    WL-CSP reliability with various solder alloys and die thicknesses by Keser, Beth, Wetz, Li, White, Jerry

    Published in Microelectronics and reliability (01-03-2004)
    “…WL-CSP is a low profile, true chip size package that is entirely built on a wafer using front-end and back-end processing. A new wafer level chip-scale package…”
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    Journal Article
  6. 6

    A Study of the Board Level Reliability of Large 16FF Wafer Level Package for RF Transceivers by Wolter, Andreas, Baumeister, Horst, Yeni, Ceren, Waidhas, Bemd, Proschwitz, Jan, Wagner, Thomas, Keser, Beth

    “…For mobile phone RF transceivers, wafer level packages (WLP) are a cost attractive solution allowing for minimum footprint and package height while providing…”
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    Conference Proceeding
  7. 7

    0.35mm pitch wafer level package board level reliability: Studying effect of ball de-population with varying ball size by Keser, Beth, Alvarado, Rey, Schwarz, Mark, Bezuk, Steve

    “…Board level reliability studies have been performed on wafer level packages (WLP) of various die sizes with 0.35mm ball pitch, SAC405 solder alloy, and two…”
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    Conference Proceeding
  8. 8

    Multi DOE Study on 28nm (RF) WLP Package to Investigate BLR Performance of Large WLP Die with 0.35mm Ball Pitch Array by Alvarado, Rey, Keser, Beth, Tong Cui, Syed, Ahmer, Xu, Steven, Roggeman, Brian

    “…Wafer Level Package (WLP) has become mainstream solution for handheld and mobile applications that require less Printed Circuit Board (PCB) footprint but comes…”
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    Conference Proceeding
  9. 9

    Board level reliability and surface mount assembly of 0.35mm and 0.3mm pitch wafer level packages by Keser, Beth, Alvarado, Rey, Choi, Alan, Schwarz, Mark, Bezuk, Steve

    “…Board level reliability studies have been performed on wafer level packages (WLP) on various die sizes with 0.35mm and 0.3mm ball pitches. The 0.35mm pitch…”
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    Conference Proceeding
  10. 10

    Interconnect reliability prediction for wafer level packages (WLP) for temperature cycle and drop load conditions by Tong Cui, Syed, Ahmer, Keser, Beth, Alvarado, Rey, Xu, Steven, Schwarz, Mark

    “…Interconnect reliability of wafer level packages (WLP) is one of the major concerns because of the direct connection of die to board without any substrate…”
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    Conference Proceeding
  11. 11

    The impact of different under bump metallurgies and redistribution layers on the electromigration of solder balls for wafer-level packaging by Hau-Riege, Christine, Keser, Beth, Alvarado, Rey, Syed, Ahmer, Yau, YouWen, Bezuk, Steve, Caffey, Kevin

    “…Electromigration performance has been characterized for lead-free solder balls in wafer-level packaging for different solder metallurgy, under bump metallurgy…”
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    Conference Proceeding
  12. 12

    Advanced Packaging: The Redistributed Chip Package by Keser, B., Amrine, C., Trung Duong, Hayes, S., Leal, G., Lytle, W., Mitchell, D., Wenzel, R.

    “…The Redistributed Chip Package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current…”
    Get full text
    Conference Proceeding
  13. 13

    Electromigration of solder balls for wafer-level packaging with different under bump metallurgy and redistribution layer thickness by Hau-Riege, Christine, Keser, Beth, You-Wen Yau, Bezuk, Steve

    “…Electromigration (EM) has been conducted on lead-free solder balls in wafer-level packages for different redistribution layer (RDL) thicknesses, under bump…”
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    Conference Proceeding
  14. 14

    A study of wafer level package board level reliability by Xu, Steven, Keser, Beth, Hau-Riege, Christine, Bezuk, Steve, You-Wen Yau

    “…Board level reliability studies have been performed on wafer level packages (WLP) with various solder ball alloys, underbump metallurgy compositions, and…”
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    Conference Proceeding
  15. 15

    Study of new alloy composition for solder balls - Identifying material properties as key leading indicators toward improved board level performance by Alvarado, Rey, Keser, Beth, Zhou, Eric, Schwarz, Mark, Bezuk, Steve, Wang, Henry, Kok-Lin Heng

    “…The quest for improved board level reliability (BLR) in wafer level packages (WLPs) motivates a characterization of novel alloys, and their impact on BLR…”
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    Conference Proceeding
  16. 16

    Electromigration studies of lead-free solder balls used for wafer-level packaging by Hau-Riege, Christine, Zang, Ricky, You-Wen Yau, Yadav, Praveen, Keser, Beth, Jong-Kai Lin

    “…Electromigration experiments have been conducted on lead-free solder balls in wafer-level packages (WLP). Lifetime distribution, Joule heating, failure mode,…”
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    Conference Proceeding
  17. 17

    Reliability evaluation on low k wafer level packages by Yadav, P., Kalchuri, S., Keser, B., Zang, R., Schwarz, M., Stone, B.

    “…Wafer Level Package (WLP) technology has seen tremendous advances in recent years and is rapidly being adopted at the 65 nm Low-K silicon node. For a true WLP,…”
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    Conference Proceeding
  18. 18

    Exploration of the design space of wafer level packaging through numerical simulation by Zhongping Bao, Burrell, J., Keser, B., Yadav, P., Kalchuri, S., Zang, Ricky

    “…Wafer Level Packaging (WLP) refers to the technology that integrated circuits are packaged at wafer level and after singulation such chips are then connected…”
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    Conference Proceeding
  19. 19

    Advanced Packaging: The Redistributed Chip Package by Keser, B., Amrine, C., Trung Duong, Hayes, S., Leal, G., Lytle, W., Mitchell, D., Wenzel, R.

    Published in IEEE transactions on advanced packaging (01-02-2008)
    “…The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current…”
    Get full text
    Journal Article
  20. 20

    Emerging technologies for wireless handsets by Pacheco, S., Keser, B., Lianjun Liu, Abrokwah, J.

    “…This paper discuss three emerging disruptive technologies that have the potential to simplify front-end module designs as the wireless handset community moves…”
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    Conference Proceeding