Search Results - "Keser, Beth"
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1
The Redistributed Chip Package: A Breakthrough for Advanced Packaging
Published in 2007 Proceedings 57th Electronic Components and Technology Conference (01-01-2007)“…The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current…”
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2
Flip-Chip Chip Scale Package (FCCSP) Process Characterization and Reliability of Coreless Thin Package with 7nm Si Technology
Published in 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) (01-05-2022)“…Advanced silicon nodes are continuously pushing the cutting edge of assembly technology with coreless thin packages used in mobile and electronic products to…”
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3
Foreword
Published in 2015 IEEE 65th Electronic Components and Technology Conference (ECTC) (01-05-2015)“…On behalf of the Program Committee and Executive Committee, it is our pleasure to welcome you to the 65th Electronic Components and Technology Conference…”
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4
Study of the Board Level Reliability Performance of a Large 0.3 mm Pitch Wafer Level Package
Published in 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) (01-05-2019)“…Board level reliability investigations have been performed on 36 mm² wafer level packages (WLP) with a 0.3 mm ball pitch. Three different solder ball alloys…”
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5
WL-CSP reliability with various solder alloys and die thicknesses
Published in Microelectronics and reliability (01-03-2004)“…WL-CSP is a low profile, true chip size package that is entirely built on a wafer using front-end and back-end processing. A new wafer level chip-scale package…”
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Journal Article -
6
A Study of the Board Level Reliability of Large 16FF Wafer Level Package for RF Transceivers
Published in 2020 IEEE 70th Electronic Components and Technology Conference (ECTC) (01-06-2020)“…For mobile phone RF transceivers, wafer level packages (WLP) are a cost attractive solution allowing for minimum footprint and package height while providing…”
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7
0.35mm pitch wafer level package board level reliability: Studying effect of ball de-population with varying ball size
Published in 2015 IEEE 65th Electronic Components and Technology Conference (ECTC) (01-05-2015)“…Board level reliability studies have been performed on wafer level packages (WLP) of various die sizes with 0.35mm ball pitch, SAC405 solder alloy, and two…”
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Multi DOE Study on 28nm (RF) WLP Package to Investigate BLR Performance of Large WLP Die with 0.35mm Ball Pitch Array
Published in 2017 IEEE 67th Electronic Components and Technology Conference (ECTC) (01-05-2017)“…Wafer Level Package (WLP) has become mainstream solution for handheld and mobile applications that require less Printed Circuit Board (PCB) footprint but comes…”
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9
Board level reliability and surface mount assembly of 0.35mm and 0.3mm pitch wafer level packages
Published in 2014 IEEE 64th Electronic Components and Technology Conference (ECTC) (01-05-2014)“…Board level reliability studies have been performed on wafer level packages (WLP) on various die sizes with 0.35mm and 0.3mm ball pitches. The 0.35mm pitch…”
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10
Interconnect reliability prediction for wafer level packages (WLP) for temperature cycle and drop load conditions
Published in 2014 IEEE 64th Electronic Components and Technology Conference (ECTC) (01-05-2014)“…Interconnect reliability of wafer level packages (WLP) is one of the major concerns because of the direct connection of die to board without any substrate…”
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11
The impact of different under bump metallurgies and redistribution layers on the electromigration of solder balls for wafer-level packaging
Published in 2014 IEEE 64th Electronic Components and Technology Conference (ECTC) (01-05-2014)“…Electromigration performance has been characterized for lead-free solder balls in wafer-level packaging for different solder metallurgy, under bump metallurgy…”
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12
Advanced Packaging: The Redistributed Chip Package
Published in 2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (01-09-2007)“…The Redistributed Chip Package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current…”
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Conference Proceeding -
13
Electromigration of solder balls for wafer-level packaging with different under bump metallurgy and redistribution layer thickness
Published in 2013 IEEE 63rd Electronic Components and Technology Conference (01-05-2013)“…Electromigration (EM) has been conducted on lead-free solder balls in wafer-level packages for different redistribution layer (RDL) thicknesses, under bump…”
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14
A study of wafer level package board level reliability
Published in 2013 IEEE 63rd Electronic Components and Technology Conference (01-05-2013)“…Board level reliability studies have been performed on wafer level packages (WLP) with various solder ball alloys, underbump metallurgy compositions, and…”
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15
Study of new alloy composition for solder balls - Identifying material properties as key leading indicators toward improved board level performance
Published in 2015 IEEE 65th Electronic Components and Technology Conference (ECTC) (01-05-2015)“…The quest for improved board level reliability (BLR) in wafer level packages (WLPs) motivates a characterization of novel alloys, and their impact on BLR…”
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16
Electromigration studies of lead-free solder balls used for wafer-level packaging
Published in 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) (01-05-2011)“…Electromigration experiments have been conducted on lead-free solder balls in wafer-level packages (WLP). Lifetime distribution, Joule heating, failure mode,…”
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17
Reliability evaluation on low k wafer level packages
Published in 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) (01-05-2011)“…Wafer Level Package (WLP) technology has seen tremendous advances in recent years and is rapidly being adopted at the 65 nm Low-K silicon node. For a true WLP,…”
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Exploration of the design space of wafer level packaging through numerical simulation
Published in 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) (01-05-2011)“…Wafer Level Packaging (WLP) refers to the technology that integrated circuits are packaged at wafer level and after singulation such chips are then connected…”
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19
Advanced Packaging: The Redistributed Chip Package
Published in IEEE transactions on advanced packaging (01-02-2008)“…The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current…”
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Journal Article -
20
Emerging technologies for wireless handsets
Published in 2007 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (01-10-2007)“…This paper discuss three emerging disruptive technologies that have the potential to simplify front-end module designs as the wireless handset community moves…”
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