Search Results - "Keng Hwa Teo"
-
1
On the Impact of Through-Silicon-Via-Induced Stress on 65-nm CMOS Devices
Published in IEEE electron device letters (01-01-2013)“…Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and…”
Get full text
Journal Article -
2
A Thermal Isolation Technique Using Through-Silicon Vias for Three-Dimensional ICs
Published in IEEE transactions on electron devices (01-03-2013)“…This brief proposes a guard ring using through-silicon vias (TSVs) to isolate thermal coupling in a 3-D integrated circuit (3-D IC). To verify this idea,…”
Get full text
Journal Article -
3
Fast Location of Opens in TSV-Based 3-D Chip Using Simple Resistor Chain
Published in IEEE transactions on electron devices (01-07-2014)“…This brief proposes an electrical method using simple resistor chain in parallel to quickly locate open circuits in a 3-D chip. This method is theoretically…”
Get full text
Journal Article -
4
A self-contained disposable cartridge microsystem for dengue viral ribonucleic acid extraction
Published in Sensors and actuators. B, Chemical (15-12-2011)“…A self-contained disposable polydimethylsiloxane (PDMS) cartridge was developed for the extraction of dengue viral ribonucleic acid (RNA) in solid phase. The…”
Get full text
Journal Article -
5
Compatibility of Dielectric Passivation and Temporary Bonding Materials for Thin Wafer Handling in 3-D TSV Integration
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01-12-2011)“…The effects of temporary bonding processes on thin wafer handling were investigated. Backside dielectric curing process was found to be a critical process for…”
Get full text
Journal Article -
6
Study of high speed interconnects of multiple dies stack structure with Through-Silicon-Via (TSV)
Published in 2010 IEEE Electrical Design of Advanced Package & Systems Symposium (01-12-2010)“…Die stacking is widely adopted for high chip count systems to reduce the requirement of substrate area. The incorporation of Through-Silicon-Via (TSV) as…”
Get full text
Conference Proceeding
-
7
Low standoff Chip to Wafer bonding
Published in 2011 IEEE 13th Electronics Packaging Technology Conference (01-12-2011)“…Industry is moving towards having module with multiple functions and capabilities in order to satisfy consumer demands. Miniaturized the package will allowed…”
Get full text
Conference Proceeding -
8
Investigation of 300 mm TSV wafer flatness with via middle scheme
Published in 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) (01-12-2012)“…Wafer flatness was monitored and investigated within TSV process development from TSV liner deposition to Cu CMP. The highest wafer bow height (455μm) was…”
Get full text
Conference Proceeding -
9
Chip to wafer bonding for three-dimensional integration of copper low K Chip by stacking process
Published in 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013) (01-12-2013)“…Industry is adopting three-dimensional integration of Cu-low k Chip with micro-solder bumps by stacking process to increase the functionality and performance…”
Get full text
Conference Proceeding -
10
TSV via-last: Optimization of multilayer dielectric stack etching
Published in 2011 IEEE 13th Electronics Packaging Technology Conference (01-12-2011)“…3D Through-silicon via (TSV) has been acknowledged as one of the future chip design technologies. In this paper, via last after Back End Of Line (BEOL) and…”
Get full text
Conference Proceeding -
11
Novel thinning/backside passivation for substrate coupling depression of 3D IC
Published in 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) (01-05-2011)“…The building blocks of the 3-D IC integration technology are Through-Silicon Via (TSV) fabrication/implementation, thin wafer handling, low-temperature…”
Get full text
Conference Proceeding -
12
Design for reliability in via middle and via last 3-D chipstacks incorporating TSVs
Published in 2010 12th Electronics Packaging Technology Conference (01-12-2010)“…Two test chips have been designed to determine the performance, yield and reliability of 3D chipstacks using Through Silicon Vias (TSVs). One of the chips uses…”
Get full text
Conference Proceeding -
13
Advanced wafer thinning and handling for through silicon via technology
Published in 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) (01-05-2011)“…This study is conducted to develop advanced wafer thinning and handling system in 50 μm thick TSV integration. Systematical investigation of the material…”
Get full text
Conference Proceeding -
14
Power integrity modeling and measurement of TSV-based 3D IC system with application to the analysis of seven-chip stack
Published in IEEE electromagnetic compatibility magazine (01-01-2016)“…This paper presents power integrity modeling and measurement of through-silicon via (TSV)-based 3D IC system. To leverage the accuracy of a full-wave approach…”
Get full text
Journal Article Magazine Article -
15
Intuitive and inexpensive method to evaluate flip chip bonding parameters of micro bump with wafer-level underfill material using glass substrate
Published in 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013) (01-12-2013)“…Flip chip bonding of chips coated with wafer-level underfill over optically transparent glass substrate allows ease of inspection of flip chip bonding quality…”
Get full text
Conference Proceeding -
16
Design of a fully-enclosed disposable bio-micro fluidic cartridge with self-contained reagents for infectious diseases diagnostic applications
Published in 2009 11th Electronics Packaging Technology Conference (01-12-2009)“…To meet the requirements of infectious diseases identification, a sealed and fully enclosed cartridge with self-contained reagents was developed. The inlet and…”
Get full text
Conference Proceeding