Search Results - "Kencke, D.L."

The Impact of Thermal Boundary Resistance in Phase-Change Memory Devices by Reifenberg, J.P., Kencke, D.L., Goodson, K.E.

“…Thermal conduction governs the writing time and energy of phase-change memory (PCM) devices. Recent measurements demonstrated large thermal resistances at the…”
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A novel Si/SiGe heterojunction pMOSFET with reduced short-channel effects and enhanced drive current by Qiqing Ouyang, Xiangdong Chen, Mudanai, S.P., Xin Wang, Kencke, D.L., Tasch, A.F., Register, L.F., Banerjee, S.K.

“…A novel Si/SiGe bandgap engineered pMOSFET structure, called a high mobility heterojunction transistor (HMHJT), is proposed. Reduced short-channel effects and…”
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A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection by Hu, C.-Y., Kencke, D.L., Banerjee, S.K., Richart, R., Bandyopadhyay, B., Moore, B., Ibok, E., Garg, S.

“…A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure…”
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A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond by Ban, I., Avci, U.E., Kencke, D.L., Chang, P.L.D.

“…A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate…”
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Floating body cell (FBC) memory for 16-nm technology with low variation on thin silicon and 10-nm BOX by Avci, U.E., Ban, I., Kencke, D.L., Chang, P.L.D.

“…A scaled planar FBC technology with undoped-body is demonstrated featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. Good agreement on retention window…”
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Band alignments in sidewall strained Si/strained SiGe heterostructures by Wang, X., Kencke, D.L., Liu, K.C., Register, L.F., Banerjee, S.K.

“…The band edge shift and splitting in an orthorhombically strained Si (OS-Si) layer grown on the sidewall of a compressively strained SiGe (CS-SiGe) alloy is…”
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A multilevel approach toward quadrupling the density of flash memory by Kencke, D.L., Richart, R., Shyam Garg, Banerjee, S.K.

“…A multilevel scheme is presented that explores the possibility of quadrupling flash EEPROM storage density. Sixteen levels (4 bits/cell) of charge are stored…”
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Floating Body Cell with Independently-Controlled Double Gates for High Density Memory by Ban, I., Avci, U.E., Shah, U., Barns, C.E., Kencke, D.L., Chang, P.

“…An aggressively scaled, self-aligned, independently controlled double-gate floating body cell (IDG FBC) is reported. This structure eases the scaling…”
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The Role of Interfaces in Damascene Phase-Change Memory by Kencke, D.L., Karpov, I.V., Johnson, B.G., Sean Jong Lee, DerChang Kau, Hudgens, S.J., Reifenberg, J.P., Savransky, S.D., Jingyan Zhang, Giles, M.D., Spadini, G.

“…Phase change memory (PCM) research has largely focused on bulk properties to evaluate cell efficiency. Now both electrical and thermal interface resistances…”
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Enhanced secondary electron injection in novel SiGe flash memory devices by Kencke, D.L., Xin Wang, Ouyang, Q., Mudanai, S., Tasch, A., Banerjee, S.K.

“…The property of SiGe layers to control channel-initiated secondary electron (CHISEL) gate current is explored for the first time using 2-D Monte Carlo…”
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A sixteen level scheme enabling 64 Mbit flash memory using 16 Mbit technology by Kencke, D.L., Richart, R., Garg, S., Banerjee, S.K.

“…Multilevel flash memories have been shown to double storage capacity without changing device dimensions. In this work, it is demonstrated for the first time…”
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Bandgap engineering in deep submicron vertical pMOSFETs by Ouyang, Q., Chen, X.D., Mudanai, S., Kencke, D.L., Tasch, A.F., Banerjee, S.K.

“…Bandgap engineering in SiGe heterojunction bipolar transistors (HBT) and high-mobility SiGe channel pMOSFETs significantly enhances the device performance…”
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Source-side barrier effects with very high-K dielectrics in 50 nm Si MOSFETs by Kencke, D.L., Chen, W., Wang, H., Mudanai, S., Ouyang, Q., Tasch, A., Banerjee, S.K.

“…High permittivity (K) gate insulators are projected for sub-100 nm Si MOSFETs since direct tunneling will likely limit SiO/sub 2/ thicknesses to 1.0-1.5 nm…”
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Tinkering with the well-tempered MOSFET: source–channel barrier modulation with high-permittivity dielectrics by Kencke, D.L., Ouyang, Q., Chen, W., Wang, H., Mudanai, S., Tasch, A., Banerjee, S.K.

“…The introduction of high permittivity (K) materials in the gate stack can change charge transport dynamics in the standard MOSFET. In this study, device…”
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The origin of secondary electron gate current: a multiple-stage Monte Carlo study for scaled, low-power flash memory by Kencke, D.L., Wang, X., Wang, H., Ouyang, Q., Jallepalli, S., Rashed, M., Maziar, C., Tasch, A., Banerjee, S.K.

“…A multiple-stage simulation procedure identifies, for the first time, the location of secondary electrons that very efficiently produce gate currents in flash…”
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Electron transport properties in novel orthorhombically-strained silicon material explored by the Monte Carlo method by Xin Wang, Kencke, D.L., Liu, K.C., Tasch, A.F., Register, L.F., Banerjee, S.K.

“…We report for the first time on the electron transport properties of simple orthorhombically-strained silicon studied by density-functional theory and Monte…”
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Two-dimensional bandgap engineering in a novel Si-SiGe pMOSFET with enhanced device performance and scalability by Ouyang, Q., Chen, X.D., Mudanai, S., Kencke, D.L., Wang, X., Tasch, A.F., Register, L.F., Banerjee, S.K.

“…Two-dimensional device simulations are used to explore the applications of bandgap engineering in improving device performance and scalability. Heterojunction…”
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Substrate-current-induced hot electron (SCIHE) injection: a new convergence scheme for flash memory by Hu, C.-Y., Kencke, D.L., Banerjee, S.K., Richart, R., Bandyopadhyay, B., Moore, B., Ibok, E., Garg, S.

“…A new convergence scheme is designed to achieve a fast speed, low power and highly reliable operation for existing flash EEPROM technology. By applying a…”
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Enhancement of drain current in vertical SiGe/Si PMOS transistors using novel CMOS technology by Liu, K.C., Ray, S.K., Oswal, S.K., Chakraborti, N.B., Chang, R.D., Kencke, D.L., Banerjee, S.K.

“…CMOS devices are being scaled for density and speed. However, scaling gate length is impeded by lithographic technology and scaling device width is limited by…”
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