Search Results - "Kayssi, A.I."

The average capacitor current method for delay calculation in MOS circuits by Kayssi, A.I.

“…The transient response of metal-oxide-semiconductor (MOS) gates is a topic covered in most textbooks on digital integrated circuits and…”
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Software linearization of DA converters by Azarian, M., Knudsen, N., Kayssi, A.I.

“…This paper presents a method for achieving increased resolution in Nyquist-rate DA converters, by using techniques from over-sampling DA converters. After…”
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J2ME end-to-end security for M-commerce by Itani, W., Kayssi, A.I.

“…This paper shows an end-to-end application-layer security solution for wireless enterprise applications using the Java 2 Platform Micro Edition (J2ME). The…”
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Ring of Masters (ROM): a new ring structure for Bluetooth scatternets by Hassan, T., Kayssi, A.I.

“…The introduction of the Bluetooth wireless technology represented a long-awaited breath by offering short-range radio communication to replace the cumbersome…”
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Macromodel construction and verification by Kayssi, A.I.

“…Macromodeling is the abstraction of information from a detailed description at a low level to a less detailed description at a higher level, with the premise…”
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Timing models for gallium arsenide direct-coupled FET logic circuits by Kayssi, A.I., Sakallah, K.A.

“…In this paper we derive delay and transition time macromodels for GaAs DCFL logic gates. The macromodels are derived by a systematic application of dimensional…”
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Macromodel simplification using dimensional analysis by Kayssi, A.I., Sakallah, K.A.

“…We present a procedure, based on dimensional analysis, to simplify macromodeling. By combining variables according to their units, simpler equations involving…”
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Delay macromodels for the timing analysis of GaAs DCFL by Kayssi, A.I., Sakallah, K.A.

“…A timing macromodel for gallium arsenide direct-coupled FET logic (GaAs DCFL) cells is derived. It calculates the delay of a cell as a function of such…”
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The design of microsupercomputers by Mudge, T.N., Brown, R.B., Birmingham, W.B., Dykstra, J.A., Kayssi, A.I., Lomax, R.J., Olukotun, O.A., Sakallah, K.A., Milano, R.A.

“…As supercomputer performance continues to grow, packaging techniques will remain critical for reducing chip-to-chip delays. In addition, higher integration…”
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SPECSA: a scalable, policy-driven, extensible, and customizable security architecture for wireless enterprise applications by Itani, W., Kayssi, A.I.

“…This paper presents SPECSA, a new, optimized, policy-driven security architecture for wireless enterprise applications. SPECSA is scalable, extensible,…”
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The design of a microsupercomputer by Mudge, T.N., Brown, R.B., Birmingham, W.P., Dykstra, J.A., Kayssi, A.I., Lomax, R.J., Olukotun, O.A., Sakallah, K.A., Milano, R.A.

“…A description is given of work to develop a prototype microcomputer that will realize the best of both the supercomputer and the microprocessor traditions. It…”
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Delay macromodels for point-to-point MCM interconnections by Kayssi, A.I., Sakallah, K.A.

“…Dimensional analysis is used to develop a macromodel for point-to-point multichip module (MCM) interconnect delay, which applies to lossless and lossy lines…”
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Signal delay in coupled, distributed RC lines in the presence of temporal proximity by Chandramouli, V., Kayssi, A.I., Sakallah, K.A.

“…With improvements in technology, accurate delay modeling of interconnects is becoming increasingly important. Due to decreasing feature sizes, the spacing…”
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Capacitor placement using genetic algorithms to reduce switching noise by Karaki, S.H., Kayssi, A.I., Abdouni, B., Raad, M.-C.

“…This work investigates the capacitor placement on a printed circuit board (PCB) to reduce the effect of simultaneous switching noise (SSN) as a genetic…”
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Analytical transient response of CMOS inverters by Kayssi, A.I., Sakallah, K.A., Burks, T.M.

“…A general formula relating the waveform at the output of a CMOS inverter to the waveform at its input is derived. The formula is applied to three cases: a step…”
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The design of a GaAs micro-supercomputer by Mudge, T.N., Brown, R.B., Birmingham, W.P., Dykstra, J.A., Kayssi, A.I., Lomax, R.J., Olukotun, O.A., Sakallah, K.A.

“…The paper is an overview of the architecture, technology and CAD tools used in the design of an experimental 250 MHz 'micro-supercomputer' which is being…”
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Delay macromodels for point-to-point MCM interconnections by Kayssi, A.I., Sakallah, K.A.

“…We develop delay macromodels for lossless as well as lossy point-to-point MCM transmission lines using a systematic model construction procedure that includes…”
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Delay modeling for GaAs DCFL circuits by Kayssi, A.I., Sakallah, K.A.

“…A timing macromodel for GaAs DCFL logic gates is derived. It circulates the delay of a gate as a function of such parameters as transistor sizes, capacitive…”
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The impact of signal transition time on path delay computation by Kayssi, A.I., Sakallah, K.A., Mudge, T.N.

“…It has been recognized for some time that nonzero signal rise and fall times contribute to gate propagation delays. Practically, however, most timing analysis…”
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GaAs RISC processors by Brown, R.B., Barker, P., Chandna, A., Huff, T.R., Kayssi, A.I., Lomax, R.J., Mudge, T.N., Nagle, D., Sakallah, K.A., Sherhart, P.J., Uhlig, R., Upton, M.

“…A simplified version of a RISC (reduced instruction set computer) microprocessor has been implemented with E/D MESFET DCFL (direct coupled FET logic) in the…”
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