Search Results - "Kavari, R."

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  1. 1

    Microstructure and reliability of copper interconnects by Changsup Ryu, Kee-Won Kwon, Loke, A.L.S., Haebum Lee, Nogami, T., Dubin, V.M., Kavari, R.A., Ray, G.W., Wong, S.S.

    Published in IEEE transactions on electron devices (01-06-1999)
    “…The effects of texture and grain structure on the electromigration lifetime of Cu interconnects are reported. Using different seed layers, [111]- and…”
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    Journal Article
  2. 2

    Composite metal etching for submicron integrated circuits by Riley, P.E., Ben-tzur, M., Kavari, R.

    “…To define metal lines for composite metal structures for integrated circuits with small pitches (<2 /spl mu/m), the etch selectivity and dimensional control…”
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    Journal Article
  3. 3

    Demonstration of scaled (⩾0.12 μm2) Pb(Zr,Ti)O3 capacitors on W plugs with Al interconnect by Summerfelt, S. R., Moise, T. S., Xing, G., Colombo, L., Sakoda, T., Gilbert, S. R., Loke, A. L. S., Ma, S., Wills, L. A., Kavari, R., Hsu, T., Amano, J., Johnson, S. T., Vestcyk, D. J., Russell, M. W., Bilodeau, S. M., van Buskirk, P.

    Published in Applied physics letters (10-12-2001)
    “…The measured switched polarization properties of integrated Pb(Zr,Ti)O3 (PZT) capacitors arrays have been found to show a small dependence on individual…”
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    Journal Article
  4. 4

    An evaluation of the HotOzone/sup TM/ process: a new post etch resist and residue removal process by Shawming Ma, Parker, R., Kavari, R., Leal, I., Boyers, D.G., Cremer, J.T.

    “…The HotOzone/sup TM/ process, a new ozone-water cleaning process for post-contact/via oxide etch or post-metal etch resist or residue removal, is evaluated…”
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    Conference Proceeding
  5. 5

    Process integration of a direct-on-metal, non-etchback, /spl kappa/=2.5 spin-on polymer for the 0.18 /spl mu/m CMOS technology node by Sum, J.C., Ray, G.W., Ma, S., Kavari, R., MacInnes, L.M., Treadwell, C.A., Dunne, J., Hacker, N.P., Figge, L.K., Hendricks, N.

    “…Process integration of a /spl kappa/=2.5 spin-on dielectric polymer into double-level metal CMOS parametric test structures at two technology nodes (0.35 /spl…”
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    Conference Proceeding
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