Search Results - "Kaushik, B.K"

Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects by Kaushik, B.K., Sarkar, S.

“…This paper deals in crosstalk analysis of a CMOS-gate-driven capacitively and inductively coupled interconnect. Alpha power-law model of a MOS transistor is…”
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Bus encoder design for crosstalk and power reduction in RLC modelled VLSI interconnects by Verma, S K, Kaushik, B K

“…Purpose – This paper aims to reduce the worst-case crosstalk effects for resistance, inductance and capacitance (RLC) interconnects using the bus encoding…”
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Channel length variation effect on performance parameters of organic field effect transistors by Mittal, Poornima, Kumar, B., Negi, Y.S., Kaushik, B.K., Singh, R.K.

“…This research paper analyzes, finite element based two dimensional device simulations for top and bottom contact organic field effect transistors (OFETs) by…”
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Effects of process variation in VLSI interconnects - a technical review by Verma, K.G, Kaushik, B.K, Singh, R

“…Purpose - Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is…”
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Temperature‐dependent modeling and performance analysis of coupled MLGNR interconnects by Rai, Mayank Kumar, Arora, Shubham, Kaushik, B.K.

“…The temperature‐dependent circuit modeling and performance in terms of propagation delay, power dissipation, and crosstalk‐induced voltage waveform at the far…”
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Memoryless nonlinearity in IT JL FinFET with spacer technology: Investigation towards reliability by Vandana, B., Mohapatra, S.K., Das, J.K., Pradhan, K.P., Kundu, A., Kaushik, B.K.

“…This work investigates the reliability assessment of high-k spacer and the effect of temperature on the device analog/RF performance for Inverted ‘T' (IT)…”
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Voltage scaling - a novel approach for crosstalk reduction in global VLSI interconnects by Kaushik, B.K, Sarkar, S, Agarwal, R.P, Joshi, R.C

“…Purpose - To analyze the effect of voltage scaling on crosstalk.Design methodology approach - Voltage scaling has been often used for reducing power…”
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ELECTRICAL TRANSPORT PROPERTIES OF PRISTINE AND IODINE DOPED POLYETHERIMIDES by Quamara, J. K., Singh, Randhir, Kaushik, B. K.

“…Electrical conduction behavior of pristine and iodine doped polyetherimides （PEI） has been investigated under both transient and steady state conditions in the…”
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VLSI interconnects and their testing: prospects and challenges ahead by Sharma, D K, Kaushik, B K, Sharma, R K

“…Purpose - The purpose of this paper is to explore the functioning of very-large-scale integration (VLSI) interconnects and modeling of interconnects and…”
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Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects by Kaushik, B.K., Sarkar, S.

“…This paper deals with crosstalk analysis of a CMOS driven capacitively and inductively coupled interconnect. The Alpha Power Law model of MOS transistor is…”
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Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards by Sharma, D.K., Sharma, R.K., Kaushik, B.K., Kumar, Pankaj

“…Purpose - This paper aims to address the various issues of board-level (off-chip) interconnects testing. A new algorithm based on the boundary scan…”
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Analytical modeling and parameter extraction of top and bottom contact structures of organic thin film transistors by Kumar, Brijesh, Kaushik, B.K., Negi, Y.S., Saxena, S., Varma, G.D.

“…This paper proposes a structure based model of an organic thin film transistor (OTFT) and analyzes its device physics. The analytical model is developed for…”
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Crosstalk Analysis of an Inductively and Capacitively Coupled Interconnect Driven by a CMOS Gate by Kaushik, B.K., Sarkar, S., Agarwal, R.P., Joshi, R.C.

“…This paper deals with crosstalk analysis of a CMOS gate driven capacitively and inductively coupled interconnect. Alpha Power Law model of MOS - transistor is…”
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Performance Analysis of Postprocessing Algorithm and Implementation on ARM7TDMI by Gupta, M., Kaushik, B.K., Chand, L.

“…Due to rapid advancement in multimedia communication a growing need emerges for the implementation of audio algorithm in real time. Filters are often used in…”
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Crosstalk Analysis of Simultaneously Switching Coupled Interconnects Driven by Unipolar Inputs through Heterogeneous Resistive Drivers by Kaushik, B.K., Sarkar, S., Agarwal, R.P., Joshi, R.C.

“…This paper focuses on waveform analysis and crosstalk peak estimation at far-end of victim line for simultaneously switching inputs with resistive drivers. A…”
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Waveform Analysis and Delay Prediction in Simultaneously Switching CMOS Gate Driven Inductively and Capacitively Coupled On-Chip Interconnects by Kaushik, B.K., Sarkar, S., Agarwal, R.P., Joshi, R.C.

“…This paper focuses on waveform analysis and delay estimation of a CMOS gate driven capacitively and inductively coupled interconnect for simultaneously…”
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Crosstalk Analysis of Simultaneously Switching Inductively and Capacitively Coupled Interconnects Driven by CMOS Gate by Kaushik, B.K., Sarkar, S., Agarwal, R.P., Joshi, R.C.

“…This paper deals in waveform analysis, crosstalk peak and delay estimation of a CMOS gate driven capacitively and inductively coupled interconnect for…”
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Terminating load dependent width optimization of global inductive VLSI interconnects by Kaushik, B.K., Sarkar, S., Agarwal, R.P.

“…In this paper interconnect width is optimized for a matched condition to reduce power and delay parameters. Width optimization is done for two sets of…”
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