Search Results - "Kashiyama, Masamori"
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Study on cyber‐security for IoT edge utilizing pattern match accelerator
Published in Electrical engineering in Japan (01-06-2021)“…A malware detection algorithm that can be embedded in IoT edge computing is proposed in this study and validated using an emulator. This algorithm, with a…”
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Journal Article -
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A Proposal of User Authentication Infrastructure for Next-Generation Telematics
Published in IEEJ transactions on electrical and electronic engineering (01-07-2010)“…To receive a telematics service, it must first be authenticated, and each automobile (or car navigation system) has typically to be linked to a particular…”
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Journal Article -
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A route search method for electric vehicles in consideration of range and locations of charging stations
Published in 2011 IEEE Intelligent Vehicles Symposium (IV) (01-06-2011)“…In this paper, we propose a new route search method for electric vehicles (EVs), which calculates a route with stopping over charging stations to have extra…”
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Conference Proceeding
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A study on user authentication infrastructure for next generation telematics
Published in 2008 IEEE International Conference on Vehicular Electronics and Safety (01-09-2008)“…To receive a telematics service, it must first be authenticated, and each automobile (or car navigation system) has typically been linked to a particular…”
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Conference Proceeding -
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A study on an authentication infrastructure between terminal and asp for next generation telematics
Published in 2008 8th International Conference on ITS Telecommunications (01-10-2008)“…To receive a telematics service, it must first be authenticated, and each automobile (or car navigation system) has typically been linked to a particular…”
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Conference Proceeding -
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Architecture and performance of the Hitachi SR2201 massively parallel processor system
Published in Proceedings - International Parallel Processing Symposium (1997)“…RISC-based Massively Parallel Processors (MPPs) often show low efficiency in real-world applications because of cache miss penalty, insufficient throughput of…”
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Conference Proceeding Journal Article -
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A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates
Published in IEEE journal of solid-state circuits (01-04-1994)“…An 18-kb RAM with 9-kgate control logic gates operating during a cycle-time of 1.5 ns has been developed. A pseudo-dual-port RAM function is achieved by a…”
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Journal Article