Search Results - "Kanemasa, A."

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  1. 1

    An Adaptive-Step Sign Algorithm for Fast Convergence of a Data Echo Canceller by Kanemasa, A., Niwa, K.

    Published in IEEE transactions on communications (01-10-1987)
    “…This paper proposes an echo cancellation algorithm that can be used for full-duplex digital data transmission over existing twisted-pair cables. The proposed…”
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    Journal Article
  2. 2

    An ISDN Subscriber Loop Transmission System Based on Echo Cancellation Technique by Kanemasa, A., Sugiyama, A., Koike, S., Koyama, T.

    “…This paper proposes an ISDN subscriber loop transmission system based on an echo cancellation technique which fully supports the CCITT recommended basic…”
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    Journal Article Conference Proceeding
  3. 3

    An adaptive filter convergence method for echo cancellation and decision feedback equalization by Kanemasa, A., Sugiyama, A.

    “…This paper proposes a new convergence method for adaptive digital filters applied to echo cancellation and decision feedback equalization. The proposed method,…”
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    Conference Proceeding
  4. 4

    24- and 120-Channel Transmultiplexers Built with New Digital Signal Processing LSI's by Maruta, R., Kanemasa, A., Sakaguchi, H., Hibino, M., Nakayama, K.

    Published in IEEE transactions on communications (01-07-1982)
    “…Two new digital transmultiplexers intended for commercial use have been developed. One transmultiplexer performs a bilateral conversion between two 12-channel…”
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    Journal Article
  5. 5

    A satellite LAN interconnecting system by Kobayashi, K., Namiki, J., Kanemasa, A., Saga, R., Watanabe, K.

    “…The authors propose a satellite LAN (local area network) interconnecting architecture which makes full use of satellite benefits and counteracts satellite…”
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    Conference Proceeding
  6. 6

    An LSI chip set for DSP hardware implementation by Kanemasa, A., Maruta, R., Nakayama, K., Sakamura, Y., Tanaka, S.

    “…This paper describes a new LSI chip set developed to provide a simple and cost-effective means for DSP hardware implementation. This chip set, consisting of…”
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    Conference Proceeding
  7. 7

    Design techniques and performance of an LSI-based 2B1Q transceiver by Arai, M., Yamaguchi, M., Nakagawa, F., Shibata, H., Kanemasa, A., Makabe, T., Koike, S.

    “…Examines a 2B1Q transceiver system which was selected as the standard for an ISDN (integrated services digital network) loop transmission systems in the US. An…”
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    Conference Proceeding
  8. 8

    An ISDN echo-cancelling transceiver chip for 2B1Q coded U-interface by Takahashi, Y., Takahara, M., Makabe, T., Inami, D., Ohno, M., Nakagawa, F., Koyama, T., Kanemasa, A., Chatani, M., Ikeda, R.

    “…A 5-V CMOS chip set used for an integrated services digital network (ISDN) U-interface transceiver is described which accomplishes 2B+D channel (144-kb/s)…”
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    Conference Proceeding
  9. 9

    STM-ATM migration plan with bridge functions by Nishihara, M., Yamaguchi, M., Kanemasa, A., Senba, T., Ono, T., Akashi, F.

    Published in IEEE Globecom, 1993 (1993)
    “…The implementation of the asynchronous transfer mode (ATM) network, as one of the vehicles for B-ISDN services, has been the subject of many enthusiastic…”
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    Conference Proceeding Journal Article