Search Results - "Kanakasabapathy, S"

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET by Loubet, N., Hook, T., Montanini, P., Yeung, C-W, Kanakasabapathy, S., Guillom, M., Yamashita, T., Zhang, J., Miao, X., Wang, J., Young, A., Chao, R., Kang, M., Liu, Z., Fan, S., Hamieh, B., Sieg, S., Mignot, Y., Xu, W., Seo, S-C, Yoo, J., Mochizuki, S., Sankarapandian, M., Kwon, O., Carr, A., Greene, A., Park, Y., Frougier, J., Galatage, R., Bao, R., Shearer, J., Conti, R., Song, H., Lee, D., Kong, D., Xu, Y., Arceo, A., Bi, Z., Xu, P., Muthinti, R., Li, J., Wong, R., Brown, D., Oldiges, P., Robison, R., Arnold, J., Felix, N., Skordas, S., Gaudiello, J., Standaert, T., Jagannathan, H., Corliss, D., Na, M-H, Knorr, A., Wu, T., Gupta, D., Lian, S., Divakaruni, R., Gow, T., Labelle, C., Lee, S., Paruchuri, V., Bu, H., Khare, M.

“…In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of…”
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FINFET technology featuring high mobility SiGe channel for 10nm and beyond by Guo, D., Karve, G., Tsutsui, G., Lim, K.-Y, Robison, R., Hook, T., Vega, R., Liu, D., Bedell, S., Mochizuki, S., Lie, F., Akarvardar, K., Wang, M., Bao, R., Burns, S., Chan, V., Cheng, K., Demarest, J., Fronheiser, J., Hashemi, P., Kelly, J., Li, J., Loubet, N., Montanini, P., Sahu, B., Sankarapandian, M., Sieg, S., Sporre, J., Strane, J., Southwick, R., Tripathi, N., Venigalla, R., Wang, J., Watanabe, K., Yeung, C. W., Gupta, D., Doris, B., Felix, N., Jacob, A., Jagannathan, H., Kanakasabapathy, S., Mo, R., Narayanan, V., Sadana, D., Oldiges, P., Stathis, J., Yamashita, T., Paruchuri, V., Colburn, M., Knorr, A., Divakaruni, R., Bu, H., Khare, M.

“…SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel…”
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Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond by Liu, Q, Yagishita, A, Loubet, N, Khakifirooz, A, Kulkarni, P, Yamamoto, T, Cheng, K, Fujiwara, M, Cai, J, Dorman, D, Mehta, S, Khare, P, Yako, K, Zhu, Y, Mignot, S, Kanakasabapathy, S, Monfray, S, Boeuf, F, Koburger, C, Sunamura, H, Ponoth, S, Reznicek, A, Haran, B, Upham, A, Johnson, R, Edge, L F, Kuss, J, Levin, T, Berliner, N, Leobandung, E, Skotnicki, T, Hane, M, Bu, H, Ishimaru, K, Kleemeier, W, Takayanagi, M, Doris, B, Sampson, R

“…We present UTBB devices with a gate length (L G ) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and…”
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A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs by Yamashita, T., Mehta, S., Basker, V. S., Southwick, R., Kumar, A., Kambhampati, R., Sathiyanarayanan, R., Johnson, J., Hook, T., Cohen, S., Li, J., Madan, A., Zhu, Z., Tai, L., Yao, Y., Chinthamanipeta, P., Hopstaken, M., Liu, Z., Lu, D., Chen, F., Khan, S., Canaperi, D., Haran, B., Stathis, J., Oldiges, P., Lin, C.-H, Narasimha, S., Bryant, A., Henson, W. K., Kanakasabapathy, S., Murali, K. V. R. M., Gow, T., McHerron, D., Bu, H., Khare, M.

“…FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However,…”
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A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels by Xie, R., Montanini, P., Akarvardar, K., Tripathi, N., Haran, B., Johnson, S., Hook, T., Hamieh, B., Corliss, D., Wang, J., Miao, X., Sporre, J., Fronheiser, J., Loubet, N., Sung, M., Sieg, S., Mochizuki, S., Prindle, C., Seo, S., Greene, A., Shearer, J., Labonte, A., Fan, S., Liebmann, L., Chao, R., Arceo, A., Chung, K., Cheon, K., Adusumilli, P., Amanapu, H. P., Bi, Z., Cha, J., Chen, H.-C, Conti, R., Galatage, R., Gluschenkov, O., Kamineni, V., Kim, K., Lee, C., Lie, F., Liu, Z., Mehta, S., Miller, E., Niimi, H., Niu, C., Park, C., Park, D., Raymond, M., Sahu, B., Sankarapandian, M., Siddiqui, S., Southwick, R., Sun, L., Surisetty, C., Tsai, S., Whang, S., Xu, P., Xu, Y., Yeh, C., Zeitzoff, P., Zhang, J., Li, J., Demarest, J., Arnold, J., Canaperi, D., Dunn, D., Felix, N., Gupta, D., Jagannathan, H., Kanakasabapathy, S., Kleemeier, W., Labelle, C., Mottura, M., Oldiges, P., Skordas, S., Standaert, T., Yamashita, T., Colburn, M., Na, M., Paruchuri, V., Lian, S., Divakaruni, R., Gow, T., Lee, S., Knorr, A., Bu, H., Khare, M.

“…We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To…”
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High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond by Liu, Q., Vinet, M., Gimbert, J., Loubet, N., Wacquez, R., Grenouillet, L., Le Tiec, Y., Khakifirooz, A., Nagumo, T., Cheng, K., Kothari, H., Chanemougame, D., Chafik, F., Guillaumet, S., Kuss, J., Allibert, F., Tsutsui, G., Li, J., Morin, P., Mehta, S., Johnson, R., Edge, L. F., Ponoth, S., Levin, T., Kanakasabapathy, S., Haran, B., Bu, H., Bataillon, J.-L, Weber, O., Faynot, O., Josse, E., Haond, M., Kleemeier, W., Khare, M., Skotnicki, T., Luning, S., Doris, B., Celik, M., Sampson, R.

“…We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (L G ) of 20nm and BOX thickness (T BOX ) of…”
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Extremely thin SOI (ETSOI) technology: Past, present, and future by Cheng, K, Khakifirooz, A, Kulkarni, P, Ponoth, S, Kuss, J, Edge, L F, Kimball, A, Kanakasabapathy, S, Schmitz, S, Reznicek, A, Adam, T, He, H, Mehta, S, Upham, A, Seo, S, Herman, J L, Johnson, R, Zhu, Y, Jamison, P, Haran, B S, Zhu, Z, Fan, S, Bu, H, Sadana, D K, Kozlowski, P, O'Neill, J, Doris, B, Shahidi, G

“…As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for…”
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Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs by Paul, A., Bryant, A., Hook, T. B., Yeh, C. C., Kamineni, V., Johnson, J. B., Tripathi, N., Yamashita, T., Tsutsui, G., Basker, V., Standaert, T. E., Faltermeier, J., Haran, B. S., Kanakasabapathy, S., Bu, H., Cho, J., Iacoponi, J., Khare, M.

“…A first time rigorous experimental study of effective current (I eff ) variability in high-volume manufacturable (HVM) 14nm Silicon-On-Insulator (SOI) FINFETs…”
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Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond by Kawasaki, H., Basker, V.S., Yamashita, T., Lin, C.-H., Zhu, Y., Faltermeier, J., Schmitz, S., Cummings, J., Kanakasabapathy, S., Adhikari, H., Jagannathan, H., Kumar, A., Maitra, K., Wang, J., Yeh, C.-C., Wang, C., Khater, M., Guillorn, M., Fuller, N., Chang, J., Chang, L., Muralidhar, R., Yagishita, A., Miller, R., Ouyang, Q., Zhang, Y., Paruchuri, V.K., Bu, H., Doris, B., Takayanagi, M., Haensch, W., McHerron, D., O'Neill, J., Ishimaru, K.

“…FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall…”
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A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM) by Beach, R., Min, T., Horng, C., Chen, Q., Sherman, P., Le, S., Young, S., Yang, K., Yu, H., Lu, X., Kula, W., Zhong, T., Xiao, R., Zhong, A., Liu, G., Kan, J., Yuan, J., Chen, J., Tong, R., Chien, J., Torng, T., Tang, D., Wang, P., Chen, M., Assefa, S., Qazi, M., DeBrosse, J., Gaidis, M., Kanakasabapathy, S., Lu, Y., Nowak, J., O'Sullivan, E., Maffitt, T., Sun, J.Z., Gallagher, W.J.

“…We have demonstrated a robust magnetic tunnel junction (MTJ) with a resistance-area product RA=8 Omega-mum 2 that simultaneously satisfies the statistical…”
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Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications by Khakifirooz, A, Cheng, K, Kulkarni, P, Cai, J, Ponoth, S, Kuss, J, Haran, B S, Kimball, A, Edge, L F, Reznicek, A, Adam, T, He, H, Loubet, N, Mehta, S, Kanakasabapathy, S, Schmitz, S, Holmes, S, Jagannathan, B, Majumdar, A, Yang, D, Upham, A, Seo, S.-C, Herman, J L, Johnson, R, Zhu, Y, Jamison, P, Zhu, Z, Vanamurth, L H, Faltermeier, J, Fan, S, Horak, D, Bu, H, Sadana, D K, Kozlowski, P, McHerron, D, O'Neill, J, Doris, B, Haensch, W, Leobondung, E, Shahidi, G

“…The authors explored some of the challenges of the extremely thin SOI technology for mainstream CMOS. Faceted RSD was used to minimize parasitic capacitance…”
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Impact of back bias on ultra-thin body and BOX (UTBB) devices by Liu, Q., Monsieur, F., Kumar, A., Yamamoto, T., Yagishita, A., Kulkarni, P., Ponoth, S., Loubet, N., Cheng, K., Khakifirooz, A., Haran, B., Vinet, M., Cai, J., Kuss, J., Linder, B., Grenouillet, L., Mehta, S., Khare, P., Berliner, N., Levin, T., Kanakasabapathy, S., Upham, A., Sreenivasan, R., Le Tiec, Y., Posseme, N., Li, J., Demarest, J., Smalley, M., Leobandung, E., Monfray, S., Boeuf, F., Skotnicki, T., Ishimaru, K., Takayanagi, M., Kleemeier, W., Bu, H., Luning, S., Hook, T., Khare, M., Shahidi, G., Doris, B., Sampson, R.

“…We present a detailed study of back bias (V bb ) impact on UTBB devices with a gate length (L G ) of 25nm and BOX thicknesses (TBOX) of 25nm and 10nm,…”
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Negative ion extraction from pulsed discharges by OVERZET, L. J, SMITH, B. A, KLEBER, J, KANAKASABAPATHY, S. K

“…Time-resolved measurements of pulsed discharges can provide information on how negative ions can be used for surface processing. Negative ions are ordinarily…”
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Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain by Cheng, K., Khakifirooz, A., Kulkarni, P., Kanakasabapathy, S., Schmitz, S., Reznicek, A., Adam, T., Zhu, Y., Li, J., Faltermeier, J., Furukawa, T., Edge, L.F., Haran, B., Seo, S.-C., Jamison, P., Holt, J., Li, X., Loesing, R., Zhu, Z., Johnson, R., Upham, A., Levin, T., Smalley, M., Herman, J., Di, M., Wang, J., Sadana, D., Kozlowski, P., Bu, H., Doris, B., O'Neill, J.

“…A new integration scheme is presented to solve device and manufacturing issues for extremely thin SOI (ETSOI) technology with high-k/metal gate. Source/drain…”
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Sub-25nm FinFET with advanced fin formation and short channel effect engineering by Yamashita, T., Basker, V. S., Standaert, T., Yeh, C-C, Yamamoto, T., Maitra, K., Lin, C-H, Faltermeier, J., Kanakasabapathy, S., Wang, M., Sunamura, H., Jagannathan, H., Reznicek, A., Schmitz, S., Inada, A., Wang, J., Adhikari, H., Berliner, N., Lee, K.-L, Kulkarni, P., Zhu, Y., Kumar, A., Bryant, A., Wu, S., Kanarsky, T., Cho, J., Mclellan, E., Holmes, S. J., Johnson, R. C., Levin, T., Demarest, J., Li, J., Oldiges, P., Arnold, J., Colburn, M., Hane, M., Mcherron, D., Paruchuri, V. K., Doris, B., Miller, R. J., Bu, H., Khare, M., O'Neill, J., Leobandung, E.

“…FinFET devices achieving N/P Ion values of 1250/950 uA/um at 100 nA/um at 1V, 1300/1000 uA/um with self-heating correction, are demonstrated, using a dual work…”
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Recent advances in MRAM technology by Gallagher, W.J., Abraham, D., Assefa, S., Brown, S.L., DeBrosse, J., Gaidis, M., Galligan, E., Gow, E., Hughes, B., Hummel, J., Kanakasabapathy, S., Kaiser, C., Lamorey, M., Maffit, T., Milkove, K., Yu Lu, Nowak, J., Rice, P., Samant, M., O'Sullivan, E., Parkin, S.S.P., Robertazzi, R., Trouilloud, P., Worledge, D., Wright, G., See-Hun Yang

“…MRAM technology offers an attractive combination of performance, density, low power, non-volatility, and write endurance. While first stand-alone MRAM products…”
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Implant approaches and challenges for 20nm node and beyond ETSOI devices by Ponoth, S., Vinet, M., Grenouillet, L., Kumar, A., Kulkarni, P., Liu, Q., Cheng, K., Haran, B., Posseme, N., Khakifirooz, A., Loubet, N., Mehta, S., Kuss, J., Destefanis, V., Berliner, N., Sreenivasan, R., Le Tiec, Y., Kanakasabapathy, S., Schmitz, S., Levin, T., Luning, S., Hook, T., Khare, M., Shahidi, G., Doris, B.

“…Two implantation based schemes were explored for ETSOI NFET devices targeted for the 20 nm node. Amorphization of the thin SOI is a key issue for the implant…”
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Full metal gate with borderless contact for 14 nm and beyond by Seo, S., Edge, L. F., Kanakasabapathy, S., Frank, M., Inada, A., Adam, L., Wang, M. M., Watanabe, K., Jamison, P., Ariyoshi, K., Sankarapandian, M., Fan, S., Horak, D., Li, J. T., Vo, T., Haran, B., Bruley, J., Hopstaken, M., Brown, S. L., Chang, J., Cartier, E. A., Park, D., Stathis, J. H., Doris, B., Divakaruni, R., Khare, M., Narayanan, V., Paruchuri, V. K.

“…Tungsten-based full metal gate (FMG) stacks that are equivalent to or better than metal-inserted poly-Si (MIPS) stack have been developed. These fully…”
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ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell by Cheng, K., Khakifirooz, A., Kulkarni, P., Ponoth, S., Haran, B., Kumar, A., Adam, T., Reznicek, A., Loubet, N., He, H., Kuss, J., Wang, M., Levin, T. M., Monsieur, F., Liu, Q., Sreenivasan, R., Cai, J., Kimball, A., Mehta, S., Luning, S., Zhu, Y., Zhu, Z., Yamamoto, T., Bryant, A., Lin, C., Naczas, S., Jagannathan, H., Edge, L. F., Allegret-Maret, S., Dube, A., Kanakasabapathy, S., Schmitz, S., Inada, A., Seo, S., Raymond, M., Zhang, Z., Yagishita, A., Demarest, J., Li, J., Hopstaken, M., Berliner, N., Upham, A., Johnson, R., Holmes, S., Standaert, T., Smalley, M., Zamdmer, N., Ren, Z., Wu, T., Bu, H., Paruchuri, V., Sadana, D., Narayanan, V., Haensch, W., O'Neill, J., Hook, T., Khare, M., Doris, B.

“…For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (L G ) and sub-100 nm contacted gate pitch for system-on-chip (SoC)…”
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A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch by Basker, V S, Standaert, T, Kawasaki, H, Yeh, C, Maitra, K, Yamashita, T, Faltermeier, J, Adhikari, H, Jagannathan, H, Wang, J, Sunamura, H, Kanakasabapathy, S, Schmitz, S, Cummings, J, Inada, A, Lin, C, Kulkarni, P, Zhu, Y, Kuss, J, Yamamoto, T, Kumar, A, Wahl, J, Yagishita, A, Edge, L F, Kim, R H, Mclellan, E, Holmes, S J, Johnson, R C, Levin, T, Demarest, J, Hane, M, Takayanagi, M, Colburn, M, Paruchuri, V K, Miller, R J, Bu, H, Doris, B, McHerron, D, Leobandung, E, O'Neill, J

“…We demonstrate the smallest FinFET SRAM cell size of 0.063 μm 2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch…”
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