Search Results - "Kaja, Endri"
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1
PaGoRi:A Scalable Parallel Golomb-Rice Decoder
Published in 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS) (03-04-2024)“…Deep Neural Networks (DNNs) have created opportunities to address real-world issues and expand the application of Artificial Intelligence (AI). Despite…”
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Parallel Golomb-Rice Decoder with 8-bit Unary Decoding for Weight Compression in TinyML Applications
Published in 2023 26th Euromicro Conference on Digital System Design (DSD) (06-09-2023)“…Due to the recent advances in AI, the requirement for Artificial Intelligence (AI) has increased exponentially in the domain of Internet of Things (IoT)…”
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3
Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs
Published in 2024 25th International Symposium on Quality Electronic Design (ISQED) (03-04-2024)“…Despite advances in register-transfer level (RTL) synthesis tools, the quality of synthesized netlists still relies on the RTL micro-architecture. This often…”
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4
An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods
Published in 2024 25th International Symposium on Quality Electronic Design (ISQED) (03-04-2024)“…As digital designs become increasingly complex, it is essential to have reliable and automated safety verification techniques. To mitigate the negative impact…”
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5
Bits, Flips and RISCs
Published in 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (03-05-2023)“…Electronic systems can be submitted to hostile environments leading to bit-flips or stuck-at faults and, ultimately, a system malfunction or failure. In…”
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6
ISA Modeling with Trace Notation for Context Free Property Generation
Published in 2021 58th ACM/IEEE Design Automation Conference (DAC) (05-12-2021)“…The scalable and extendable RISC-V ISA introduced a new level of flexibility in designing highly customizable processors. This flexibility in processor designs…”
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Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models
Published in 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (06-10-2021)“…Safety-critical designs used in automotive applications need to ensure reliable operations even under hostile operating conditions. As these designs grow in…”
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Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V
Published in 2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (08-10-2024)“…As the semiconductor industry rapidly expands, there is a need for new development methods, especially in the domain of safety-critical designs. The ISO 26262…”
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An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs
Published in 2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (08-10-2024)“…The trend toward scaling and more complex fabrication techniques in digital circuit design often leads to numerous faults within Integrated Circuits (ICs). To…”
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10
MetaFS: Model-driven Fault Simulation Framework
Published in 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (19-10-2022)“…The adoption of new technologies by the automotive industry drives the need for electronic component suppliers to assess and scrutinize the risk of…”
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11
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection
Published in 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC) (03-10-2022)“…While semiconductors are becoming more efficient generation after generation, the continuous technology scaling leads to numerous reliability issues due,…”
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12
Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation
Published in 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC) (03-10-2022)“…Safety-critical designs need to ensure reliable operations even under a hostile working environment with a certain degree of confidence. Continuous technology…”
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MetFI: Model-driven Fault Simulation Framework
Published 27-04-2022“…Safety-critical designs need to ensure reliable operations under hostile conditions with a certain degree of confidence. The continuously higher complexity of…”
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Journal Article -
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Automated SoC Hardening with Model Transformation
Published in 2020 17th Biennial Baltic Electronics Conference (BEC) (06-10-2020)“…Fault tolerance enables the system to avoid threats (fail-safe) or continue with its safe operational functionality even in the presence of random faults. This…”
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Conference Proceeding