Search Results - "Kai Chong Chan"
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1
Underfill selection methodology for fine pitch Cu/low-k FCBGA packages
Published in Microelectronics and reliability (01-02-2009)“…A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid…”
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Journal Article -
2
Characterizations for eWLB (Embedded Wafer Level Ball Grid Array) Antenna in Molded Package Integrations in 77GHz Automotive Applications
Published in 2023 24th European Microelectronics and Packaging Conference & Exhibition (EMPC) (11-09-2023)“…The worldwide IC market has had a significant growth rate in recent years, driving diversified package solutions in the segments of communication, computing,…”
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Conference Proceeding -
3
Design, assembly and reliability of large die and fine-pitch Cu/low- k flip chip package
Published in Microelectronics and reliability (01-07-2010)“…This paper reports the design, assembly and reliability assessment of 21 × 21 mm 2 Cu/low- k flip chip (65 nm node) with 150 μm bump pitch and high bump…”
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Journal Article -
4
Underfill Selection, Characterization, and Reliability Study for Fine-Pitch, Large Die Cu/Low-K Flip Chip Package
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01-03-2011)“…This paper presents a systematic underfill selection and characterization methods for 21 ×21 mm 2 Cu/low-K flip chip packages (65 nm technology) with 150 μm…”
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Journal Article -
5
Enabling fine pitch Cu & Ag alloy wire bond assessment for 28nm ultra low-k structure
Published in 2014 IEEE 64th Electronic Components and Technology Conference (ECTC) (01-05-2014)“…The use of copper wire in IC packaging has been growing steadily driven by cost effectiveness. However, there are concerns and issues that prevent or delay…”
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Conference Proceeding -
6
Study on low-cost QFN packages for high-frequency applications
Published in 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) (01-12-2012)“…Quad flat no-lead (QFN) packages have found wide applications in RF and high-speed digital systems. The purpose of this paper is to study high-frequency…”
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Conference Proceeding -
7
Copper wire bond analysis: Pad design effects and process considerations
Published in 2012 IEEE 62nd Electronic Components and Technology Conference (01-05-2012)“…In this paper, the fundamental understanding of copper (Cu) wire bonding process, and its interaction with the die bond pad surface and structure will be…”
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Conference Proceeding -
8
Dicing Blade Characterization Using Nano-indentation
Published in 2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC) (07-12-2021)“…In this paper, the widely used nano-indentation technique is employed to characterize the mechanical properties of dicing blade. The dicing blade is a…”
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Conference Proceeding -
9
Structural Design and Optimization of 65nm Cu/low-k Flipchip Package
Published in 2007 9th Electronics Packaging Technology Conference (01-12-2007)“…The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k…”
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Conference Proceeding -
10
A Systematic Underfill Selection Methodology for Fine Pitch Cu/Low-k FCBGA Package
Published in 2007 9th Electronics Packaging Technology Conference (01-12-2007)“…In this paper, a systematic underfill selection approach has been presented to characterize and identify favorable underfill encapsulants for 21 Х 21mm 2 flip…”
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Conference Proceeding -
11
Effects of annealing of proton-exchanged LiNbO3 waveguides
Published in Japanese journal of applied physics (1992)Get full text
Conference Proceeding -
12
Design, Assembly and Reliability of Large Die (21 x 21mm2) and Fine-pitch (150pm) Cu/Low-K Flip Chip Package
Published in 2008 10th Electronics Packaging Technology Conference (01-12-2008)“…This paper focused on design, assembly and reliability assessments of 21 × 21 mm 2 Cu/Low-K Flip Chip (65 nm technology) with 150 ¿m bump pitch. Metal…”
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Conference Proceeding