Search Results - "Kahne, Brian"
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MINIME: Pattern-Aware Multicore Benchmark Synthesizer
Published in IEEE transactions on computers (01-08-2015)“…We present a novel automated multicore benchmark synthesis framework with characterization and generation components. Our framework uses parallel patterns in…”
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Journal Article -
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Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications
Published in IEEE computer architecture letters (01-07-2018)“…Multicores increasingly deploy spatial execution of safety-critical applications that demand a deterministic, resilient, and secure environment to meet the…”
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Journal Article -
3
MINIME-validator: Validating hardware with synthetic parallel testcases
Published in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 (01-03-2017)“…Programming of multicore architectures with large number of cores is a huge burden on the programmer. Parallel patterns ease this burden by presenting the…”
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Conference Proceeding -
4
MBET: Resilience Improvement Method for DNNs
Published in 2022 IEEE International Conference On Artificial Intelligence Testing (AITest) (01-08-2022)“…Deep neural network (DNN) accelerators become a large study field. Low voltage DNN accelerators are designed to achieve high throughput and reduce energy…”
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Conference Proceeding -
5
Simulated Quantization, Real Power Savings
Published in 2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW) (01-06-2022)“…Reduced precision hardware-based matrix multiplication accelerators are commonly employed to reduce power consumption of neural network inference. Multiplier…”
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Conference Proceeding -
6
Functional Validation of a New Network Switch Architecture Using Rapid Prototyping Techniques
Published in 2013 14th International Workshop on Microprocessor Test and Verification (01-12-2013)“…When developing a new architecture with a new programming model, not only must performance be taken into account, but the programming model itself must also be…”
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Conference Proceeding -
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Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging
Published in 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS) (01-05-2017)“…Shared Memory stands out as a sine qua non for parallel programming of many commercial and emerging multicore processors. It optimizes patterns of…”
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Conference Proceeding -
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Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication
Published in 2015 IEEE International Conference on Networking, Architecture and Storage (NAS) (01-08-2015)“…Software IP forwarding routers provide flexibility, programmability and extensibility, while enabling fast deployment. The key question is whether they can…”
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Conference Proceeding -
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Using software architectural patterns for synthetic embedded multicore benchmark development
Published in 2012 IEEE International Symposium on Workload Characterization (IISWC) (01-11-2012)“…Benchmarks capture the essence of many important real-world applications and allow performance, and power analysis while developing new systems. Synthetic…”
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Conference Proceeding -
10
Retiming Verification Using Sequential Equivalence Checking
Published in 2005 Sixth International Workshop on Microprocessor Test and Verification (01-11-2005)“…High performance designs must conform to stringent timing requirements. Designers frequently utilize low-level optimization techniques and develop many…”
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Conference Proceeding -
11
An Introduction to the Plasma Language
Published in 2005 Sixth International Workshop on Microprocessor Test and Verification (01-11-2005)“…The ability to enhance single-thread performance, such as by increasing clock frequency, is reaching a point of diminishing returns: power is becoming a…”
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Conference Proceeding -
12
Performance analysis for chipsets and systems
Published in 1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305) (1999)“…Plasma is a new tool for modeling the timing of chipsets and other system components. Modeling chipsets is in some ways more difficult than modeling…”
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Conference Proceeding