Search Results - "Kahne, Brian"

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  1. 1

    MINIME: Pattern-Aware Multicore Benchmark Synthesizer by Deniz, Etem, Sen, Alper, Kahne, Brian, Holt, Jim

    Published in IEEE transactions on computers (01-08-2015)
    “…We present a novel automated multicore benchmark synthesis framework with characterization and generation components. Our framework uses parallel patterns in…”
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    Journal Article
  2. 2

    Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications by Omar, Hamza, Dogan, Halit, Kahne, Brian, Khan, Omer

    Published in IEEE computer architecture letters (01-07-2018)
    “…Multicores increasingly deploy spatial execution of safety-critical applications that demand a deterministic, resilient, and secure environment to meet the…”
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    Journal Article
  3. 3

    MINIME-validator: Validating hardware with synthetic parallel testcases by Sen, Alper, Deniz, Etem, Kahne, Brian

    “…Programming of multicore architectures with large number of cores is a huge burden on the programmer. Parallel patterns ease this burden by presenting the…”
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    Conference Proceeding
  4. 4

    MBET: Resilience Improvement Method for DNNs by Buldu, Abdullah Murat, Sen, Alper, Swaminathan, Karthik, Kahne, Brian

    “…Deep neural network (DNN) accelerators become a large study field. Low voltage DNN accelerators are designed to achieve high throughput and reduce energy…”
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    Conference Proceeding
  5. 5

    Simulated Quantization, Real Power Savings by van Baalen, Mart, Kahne, Brian, Mahurin, Eric, Kuzmin, Andrey, Skliar, Andrii, Nagel, Markus, Blankevoort, Tijmen

    “…Reduced precision hardware-based matrix multiplication accelerators are commonly employed to reduce power consumption of neural network inference. Multiplier…”
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    Conference Proceeding
  6. 6

    Functional Validation of a New Network Switch Architecture Using Rapid Prototyping Techniques by Kahne, Brian, Holt, Jim

    “…When developing a new architecture with a new programming model, not only must performance be taken into account, but the programming model itself must also be…”
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    Conference Proceeding
  7. 7

    Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging by Dogan, Halit, Hijaz, Farrukh, Ahmad, Masab, Kahne, Brian, Wilson, Peter, Khan, Omer

    “…Shared Memory stands out as a sine qua non for parallel programming of many commercial and emerging multicore processors. It optimizes patterns of…”
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    Conference Proceeding
  8. 8

    Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication by Hijaz, Farrukh, Kahne, Brian, Wilson, Peter, Khan, Omer

    “…Software IP forwarding routers provide flexibility, programmability and extensibility, while enabling fast deployment. The key question is whether they can…”
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    Conference Proceeding
  9. 9

    Using software architectural patterns for synthetic embedded multicore benchmark development by Deniz, Etem, Sen, Alper, Holt, Jim, Kahne, Brian

    “…Benchmarks capture the essence of many important real-world applications and allow performance, and power analysis while developing new systems. Synthetic…”
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    Conference Proceeding
  10. 10

    Retiming Verification Using Sequential Equivalence Checking by Kahne, B., Abadir, M.

    “…High performance designs must conform to stringent timing requirements. Designers frequently utilize low-level optimization techniques and develop many…”
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    Conference Proceeding
  11. 11

    An Introduction to the Plasma Language by Kahne, B., Gupta, A., Wilson, P., Dutt, N.

    “…The ability to enhance single-thread performance, such as by increasing clock frequency, is reaching a point of diminishing returns: power is becoming a…”
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    Conference Proceeding
  12. 12

    Performance analysis for chipsets and systems by Lutz, D.R., Kahne, B.

    “…Plasma is a new tool for modeling the timing of chipsets and other system components. Modeling chipsets is in some ways more difficult than modeling…”
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    Conference Proceeding