Search Results - "Kaczer, B."

Refine Results
  1. 1

    Defect profiling in FEFET Si:HfO2 layers by O'Sullivan, B. J., Putcha, V., Izmailov, R., Afanas'ev, V., Simoen, E., Jung, T., Higashi, Y., Degraeve, R., Truijen, B., Kaczer, B., Ronchi, N., McMitchell, S., Banerjee, K., Clima, S., Breuil, L., Van den Bosch, G., Linten, D., Van Houdt, J.

    Published in Applied physics letters (16-11-2020)
    “…Ferroelectric Si-doped HfO2 is a promising candidate for future generation memory devices. However, such devices are vulnerable to significant threshold…”
    Get full text
    Journal Article
  2. 2

    Investigation of Imprint in FE-HfO₂ and Its Recovery by Higashi, Y., Kaczer, B., Verhulst, A. S., O'Sullivan, B. J., Ronchi, N., McMitchell, S. R. C., Banerjee, K., Piazza, L. Di, Suzuki, M., Linten, D., Van Houdt, J.

    Published in IEEE transactions on electron devices (01-11-2020)
    “…Ferroelectric (FE)-HfO 2 -based FETs (FEFETs) are one of the most promising candidates for emerging memories. However, the FE material suffers from a unique…”
    Get full text
    Journal Article
  3. 3

    Towards Complete Recovery of Circuit Degradation by Annealing With On-Chip Heaters by Diaz-Fortuny, J., Saraza-Canflanca, P., Lofrano, M., Bury, E., Degraeve, R., Kaczer, B.

    Published in IEEE electron device letters (01-02-2023)
    “…This work reports an on-chip heater structure fabricated in the Front End of Line (FEOL) on a versatile ring-oscillator (RO) array utilized to conduct…”
    Get full text
    Journal Article
  4. 4

    Unveiling the Vulnerability of Oxide-Breakdown-Based PUF by Saraza-Canflanca, P., Fodor, F., Diaz-Fortuny, J., Gierlichs, B., Degraeve, R., Kaczer, B., Verbauwhede, I., Bury, E.

    Published in IEEE electron device letters (01-05-2024)
    “…This work reports a potential vulnerability of an oxide-breakdown-based Physical Unclonable Function (PUF). This generates a unique chip key based on the…”
    Get full text
    Journal Article
  5. 5

    Trapping of Hot Carriers in the Forksheet FET Wall: A TCAD Study by Vandemaele, M., Kaczer, B., Tyaginov, S., Franco, J., Bury, E., Chasin, A., Makarov, A., Hellings, G., Groeseneken, G.

    Published in IEEE electron device letters (01-02-2023)
    “…We simulate the spatial profile of trapped charge in the forksheet FET wall under hot-carrier stress by calculating carrier distribution functions and using a…”
    Get full text
    Journal Article
  6. 6

    Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics by Xiang, Y., Bardon, M. Garcia, Kaczer, B., Alam, Md Nur K., Ragnarsson, L.-A., Kaczmarek, K., Parvais, B., Groeseneken, G., Van Houdt, J.

    Published in IEEE transactions on electron devices (01-04-2021)
    “…The (doped-)hafnia-based' ferroelectric FET (FeFET) is a promising candidate for low-power nonvolatile memories and shows potential use as a steep-slope…”
    Get full text
    Journal Article
  7. 7

    Statistics of Multiple Trapped Charges in the Gate Oxide of Deeply Scaled MOSFET Devices-Application to NBTI by Kaczer, B, Roussel, Ph J, Grasser, T, Groeseneken, G

    Published in IEEE electron device letters (01-05-2010)
    “…The statistical distribution of negative bias temperature instability (NBTI) in deca-nanometer p-channel FETs is discussed. An exponential distribution of…”
    Get full text
    Journal Article
  8. 8

    Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions by Franco, J., Arimura, H., de Marneffe, J.-F., Brus, S., Ritzenthaler, R., Croes, K., Kaczer, B., Horiguchi, Naoto

    Published in IEEE transactions on electron devices (01-12-2023)
    “…Low thermal budget gate stack fabrication is a key enabler for upcoming CMOS technology innovations, such as sequential-3-D integration and CFETs. In this…”
    Get full text
    Journal Article
  9. 9

    Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis by Asanovski, R., Arimura, H., de Marneffe, J.-F., Palestri, P., Horiguchi, N., Kaczer, B., Selmi, L., Franco, J.

    Published in IEEE transactions on electron devices (01-03-2024)
    “…This study presents a comprehensive investigation of defects in the gate-stack of low-thermal budget replacement metal gate (RMG) MOSFETs treated with novel…”
    Get full text
    Journal Article
  10. 10

    Impact of Charge Trapping and Depolarization on Data Retention Using Simultaneous P-V and I-V in HfO₂-Based Ferroelectric FET by Higashi, Y., Ronchi, N., Kaczer, B., Alam, Md Nur K., O'Sullivan, B. J., Banerjee, K., McMitchell, S. R. C., Breuil, L., Walke, A., Van den Bosch, G., Linten, D., Van Houdt, J.

    Published in IEEE transactions on electron devices (01-09-2021)
    “…The ferroelectric (FE)-HfO 2 -based field-effect transistor (FEFET) is a promising candidate for emerging memory. However, data retention (DR) loss has been…”
    Get full text
    Journal Article
  11. 11

    Evidence That Two Tightly Coupled Mechanisms Are Responsible for Negative Bias Temperature Instability in Oxynitride MOSFETs by Grasser, T., Kaczer, B.

    Published in IEEE transactions on electron devices (01-05-2009)
    “…Negative bias temperature instability (NBTI) is a serious reliability concern for pMOS transistors. Although discovered more than 40 years ago, the phenomenon…”
    Get full text
    Journal Article
  12. 12

    A HydroDynamic Model for Trap-Assisted Tunneling Conduction in Ovonic Devices by Buscemi, F., Piccinini, E., Vandelli, L., Nardi, F., Padovani, A., Kaczer, B., Garbin, D., Clima, S., Degraeve, R., Kar, G. S., Tavanti, F., Slassi, A., Calzolari, A., Larcher, L.

    Published in IEEE transactions on electron devices (01-04-2023)
    “…Electrical conduction in ovonic threshold switching (OTS) devices is described by introducing a new physical model where the multiphonon trap-assisted…”
    Get full text
    Journal Article
  13. 13

    Variability in Planar FeFETs-Channel Percolation Impact by Kaczmarek, K., Bardon, M. Garcia, Xiang, Y., Ronchi, N., Ragnarsson, L.-A., Celano, U., Banerjee, K., Kaczer, B., Groeseneken, G., Houdt, J. Van

    Published in IEEE transactions on electron devices (01-07-2023)
    “…We examine the origins of threshold voltage (<inline-formula> <tex-math notation="LaTeX">\textit{V}_{\text{TH}}\text{)}</tex-math> </inline-formula>…”
    Get full text
    Journal Article
  14. 14
  15. 15

    Superior NBTI in High- k SiGe Transistors–Part I: Experimental by Waltl, M., Rzepa, G., Grill, A., Goes, W., Franco, J., Kaczer, B., Witters, L., Mitard, J., Horiguchi, N., Grasser, T.

    Published in IEEE transactions on electron devices (01-05-2017)
    “…SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias…”
    Get full text
    Journal Article
  16. 16

    The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability by Grasser, T, Reisinger, H, Wagner, P, Schanovsky, F, Goes, W, Kaczer, B

    “…We introduce a new method to analyze the statistical properties of the defects responsible for the ubiquitous recovery behavior following negative bias…”
    Get full text
    Conference Proceeding
  17. 17

    Low leakage Ru-strontium titanate-Ru metal-insulator-metal capacitors for sub-20 nm technology node in dynamic random access memory by Popovici, M., Swerts, J., Redolfi, A., Kaczer, B., Aoulaiche, M., Radu, I., Clima, S., Everaert, J.-L., Van Elshocht, S., Jurczak, M.

    Published in Applied physics letters (24-02-2014)
    “…Improved metal-insulator-metal capacitor (MIMCAP) stacks with strontium titanate (STO) as dielectric sandwiched between Ru as top and bottom electrode are…”
    Get full text
    Journal Article
  18. 18

    Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures by Grill, A., Bury, E., Michl, J., Tyaginov, S., Linten, D., Grasser, T., Parvais, B., Kaczer, B., Waltl, M., Radu, I.

    “…In this work, we present time-zero variability and degradation data obtained from a large set of on-chip devices in specifically designed arrays, from room…”
    Get full text
    Conference Proceeding
  19. 19

    Process implications on the stability and reliability of 300 mm FAB MoS2 field-effect transistors by Illarionov, Yu. Yu, Karl, A., Smets, Q., Kaczer, B., Knobloch, T., Panarella, L., Schram, T., Brems, S., Cott, D., Asselberghs, I., Grasser, T.

    Published in NPJ 2D materials and applications (02-02-2024)
    “…Recent advances in fabricating field-effect transistors with MoS 2 and other related two-dimensional (2D) semiconductors have inspired the industry to begin…”
    Get full text
    Journal Article
  20. 20

    Superior NBTI in High-k SiGe Transistors-Part II: Theory by Waltl, M., Rzepa, G., Grill, A., Goes, W., Franco, J., Kaczer, B., Witters, L., Mitard, J., Horiguchi, N., Grasser, T.

    Published in IEEE transactions on electron devices (01-05-2017)
    “…The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device…”
    Get full text
    Journal Article