Search Results - "KURD, Nasser"

A Fast Startup Crystal Oscillator Using Impedance Guided Chirp Injection in 22 nm FinFET CMOS by Luo, Hao, Kundu, Somnath, Huusari, Timo, Shahraini, Sarah, Alban, Eduardo, Mix, Jason, Kurd, Nasser, Abdel-Moneum, Mohamed, Carlton, Brent

“…An Impedance Guided Chirp Injection (IGCI) oscillator-based fast startup technique is proposed in this work demonstrating startup time between 5 and 100…”
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Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking by Kurd, N., Mosalikanti, P., Neidengard, M., Douglas, J., Kumar, R.

“…This paper describes the core and I/O clocking architecture of the next generation Intel reg Coretrade micro-architecture processor (Nehalem), designed on a 45…”
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A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup by Kundu, Somnath, Huusari, Timo, Luo, Hao, Agrawal, Abhishek, Alban, Eduardo, Shahraini, Sarah, Xiong, Thao, Lake, Dan, Pellerano, Stefano, Mix, Jason, Kurd, Nasser, Abdel-moneum, Mohamed, Carlton, Brent

“…A high-performance clock generator with extremely low jitter, area, and power consumption is the key building block in the emerging Internet of Things (IoT) to…”
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A Family of 32 nm IA Processors by Kurd, Nasser A, Bhamidipati, Subramani, Mozak, Chris, Miller, Jeffrey L, Mosalikanti, Praveen, Wilson, Timothy M, El-Husseini, Ali M, Neidengard, Mark, Aly, Ramy E, Nemani, Mahadev, Chowdhury, Muntaquim, Kumar, Rajesh

“…Westmere is the latest IA processor family for mobile, desktop and server market segments, implemented on Intel's second-generation high-k metal gate 32 nm…”
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Haswell: A Family of IA 22 nm Processors by Kurd, Nasser, Chowdhury, Muntaquim, Burton, Edward, Thomas, Thomas P., Mozak, Christopher, Boswell, Brent, Mosalikanti, Praveen, Neidengard, Mark, Deval, Anant, Khanna, Ashish, Chowdhury, Nasirul, Rajwar, Ravi, Wilson, Timothy M., Kumar, Rajesh

“…We describe the 4th Generation Intel® Core™ processor family (codenamed "Haswell") implemented on Intel® 22 nm technology and intended to support form factors…”
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Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control by Huang, Chi-Hsiang, Chen, Yidong, Sun, Xun, Mandal, Arindam, Pamula, Venkata Rajesh, Kurd, Nasser, Sathe, Visvesh S.

“…Single-inductor multiple-output (SIMO) voltage regulators allow multiple voltage domains to share a single inductor, thus representing a domain-scalable…”
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A Compact First-Order \Sigma\Delta Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process by Oshita, Takao, Shor, Joseph, Duarte, David E., Kornfeld, Avner, Geannopoulos, George L., Douglas, Jonathan, Kurd, Nasser

“…On complex system-on-chips (SOCs), a compact on-die analog-to-digital converter (ADC) is required in high-volume testing, in order to reduce the test time and…”
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A Compact First-Order Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process by Oshita, Takao, Shor, Joseph, Duarte, David E, Kornfeld, Avner, Geannopoulos, George L, Douglas, Jonathan, Kurd, Nasser

“…On complex system-on-chips (SOCs), a compact on-die analog-to-digital converter (ADC) is required in high-volume testing, in order to reduce the test time and…”
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A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS by Shen, Kuan-Yueh, Syed Farooq, Syed Feruz, Fan, Yongping, Nguyen, Khoa Minh, Wang, Qi, Neidengard, Mark L., Kurd, Nasser, Elshazly, Amr

“…This paper presents a PLL supporting diverse low-power clocking needs including wide input (6-200 MHz) and output (0.15-5 GHz) frequency ranges and SSC…”
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A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS by Luo, Hao, Kundu, Somnath, Lee, Chun, Jain, Rinkle, Shahraini, Sarah, Alban, Eduardo, Huusari, Timo, Mix, Jason, Kurd, Nasser, Abdel-moneum, Mohamed, Carlton, Brent

“…Low power mobile and edge computing systems requires fast wakeup for pleasant end user experience and for efficient data processing. Fast start up oscillators…”
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29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop Mitigation by Mosalikanti, Praveen, Wang, Qi, Shen, Kuan-Yueh James, Neidengard, Mark, Farooq, Syed Feruz Syed, Grossnickle, Vaughn, Kurd, Nasser

“…We present a 0.4-to-6.5GHz Frequency Locked Loop (FLL) implemented in 10nm CMOS, targeting high performance SoCs that require uninterrupted, overshoot-free…”
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Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging by Tschanz, James, Kim, Nam Sung, Dighe, Saurabh, Howard, Jason, Ruhl, Gregory, Vangal, Sriram, Narendra, Siva, Hoskote, Yatin, Wilson, Howard, Lam, Carol, Shuman, Matthew, Tokunaga, Carlos, Somasekhar, Dinesh, Tang, Stephen, Finan, David, Karnik, Tanay, Borkar, Nitin, Kurd, Nasser, De, Vivek

“…Temperature, voltage, and current sensors monitor the operation of a TCP/IP offload accelerator engine fabricated in 90nm CMOS, and a control unit dynamically…”
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A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology by Lotfy, Amr, Farooq, Syed Feruz Syed, Wang, Qi S., Yaldiz, Soner, Mosalikanti, Praveen, Kurd, Nasser

“…This paper presents a System-Verilog behavioral model for charge-pump PLLs based on piece-wise constant (PWC) real number modeling and table lookup. The…”
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A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor by Kurd, N.A., Barkarullah, J.S., Dizon, R.O., Fletcher, T.D., Madland, P.D.

“…Core and I/O clock design for the Pentium(R) 4 microprocessor is described. Two phase-locked loops generate core and I/O clocks supporting concurrent multiple…”
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19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS by Shen, Kuan-Yueh James, Farooq, Syed Feruz Syed, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Elshazly, Amr, Kurd, Nasser

“…With recent advancements in SoC integration, modern SoC architectures can employ more than 20 PLLs [1]. To address SoC clocking needs with an ever reducing…”
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Westmere: A family of 32nm IA processors by Kurd, N.A., Bhamidipati, S., Mozak, C., Miller, J.L., Wilson, T.M., Nemani, M., Chowdhury, M.

“…Westmere is a family of next-generation IA processors for mobile, desktop and server segments on a second-generation high-¿ metalgate 32 nm process offering…”
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5.9 Haswell: A family of IA 22nm processors by Kurd, Nasser, Chowdhury, Muntaquim, Burton, Edward, Thomas, Thomas P., Mozak, Christopher, Boswell, Brent, Lal, Manoj, Deval, Anant, Douglas, Jonathan, Elassal, Mahmoud, Nalamalpu, Ankireddy, Wilson, Timothy M., Merten, Matthew, Chennupaty, Srinivas, Gomes, Wilfred, Kumar, Rajesh

“…The 4th Generation Intel® Core™ processor, codenamed Haswell, is a family of products implemented on Intel 22nm Tri-gate process technology [1]. The primary…”
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Next Generation Intel® CoreTM Micro-Architecture (Nehalem) Clocking by KURD, Nasser, MOSALIKANTI, Praveen, NEIDENGARD, Mark, DOUGLAS, Jonathan, KUMAR, Rajesh

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Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses by Ghoneima, M.M., Khellah, M.M., Tschanz, J., Yibin Ye, Kurd, N., Barkatullah, J.S., Nimmagadda, S., Ismail, Y., De, V.K.

“…This paper purposes a bus architecture called skewed repeater bus (SRB) for reducing on-chip interconnect energy in microprocessors. By introducing a dynamic…”
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Modeling the response of Bang-Bang digital PLLs to phase error perturbations by Abdelfattah, M., Ghoneima, M., Ismail, Y. I., Lotfy, A., Abdel-moneum, M., Kurd, N. A., Taylor, G.

“…Bang-Bang phase locked loops (BB-PLLs) offer a low power implementation of digital PLLs. However, the response of BB-PLLs, unlike linear PLLs, depends on the…”
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