Search Results - "KODAMA, Chikaaki"
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Development of a Lithography Simulation Tool Set in Various Optical Conditions for Source Mask Optimization
Published in IEEE access (2024)“…Resolution Enhancement Techniques (RETs) in optical lithography have become essential for achieving the continuous shrinkage of technology nodes. The primary…”
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Effective two-dimensional pattern generation for self-aligned double patterning
Published in 2015 IEEE International Symposium on Circuits and Systems (ISCAS) (01-05-2015)“…In nano-scale systems, design for manufacturability is essentially required. For sub 20 nm technology node, Self-Aligned Double Patterning (SADP) is an…”
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Conference Proceeding -
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A fast algorithm for rectilinear block packing based on selected sequence-pair
Published in Integration (Amsterdam) (01-04-2007)“…In this paper, we present a method of rectilinear block packing using selected sequence-pair (SSP), a rectangle packing representation. We also propose a fast…”
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Lithography hotspot detection by two-stage cascade classifier using histogram of oriented light propagation
Published in 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) (01-01-2017)“…In advanced semiconductor-process technology, the ability to detect and repair lithography hotspots, which can affect printability, is essential. In this…”
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Conference Proceeding -
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A fast process variation and pattern fidelity aware mask optimization algorithm
Published in 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (01-11-2014)“…With the continuous shrinking of minimum feature sizes beyond current 193nm wavelength for optical micro lithography, the electronic industry relies on…”
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Conference Proceeding -
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Subresolution Assist Feature Generation With Supervised Data Learning
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-06-2018)“…Subresolution assist feature (SRAF) generation is a very important resolution enhancement technique to improve yield in modern semiconductor manufacturing…”
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A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling
Published in IEEE transactions on very large scale integration (VLSI) systems (01-03-2017)“…With the continuous shrinkage of advanced technology nodes into the sub-16-nm regime, optical proximity correction (OPC) is still the main stream to preserve…”
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A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation
Published in 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01-03-2016)“…Aggressive Optical Proximity Correction (OPC) has been widely adopted in optical lithography to preserve circuit performance for sub-20nm technology nodes…”
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Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-05-2015)“…Although self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all…”
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Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern
Published in 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01-03-2016)“…A routing grid for Self-Aligned Quadruple Patterning (SAQP) helps to find a valid routing of SAQP, but it is not easy to find it. The routing of SAQP on the…”
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Conference Proceeding Journal Article -
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Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-04-2007)“…In recent high-performance analog integrated circuit design, it is often required to place some cells symmetrically to a horizontal or vertical axis. Balasa et…”
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Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control
Published in 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) (01-01-2013)“…Although Self-Aligned Double and Quadruple Patterning (SADP, SAQP) have become the most promising processes for sub-20 nm and sub-14 nm node advanced…”
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Conference Proceeding -
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Manufacturability-aware mask assignment in multiple patterning lithography
Published in 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (01-10-2016)“…Due to the progress of the process technology, multiple patterning lithography (MPL) is one of the most promising techniques in the 22 nm logic node and…”
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Conference Proceeding -
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Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography
Published in The 20th Asia and South Pacific Design Automation Conference (01-01-2015)“…One of the most promising techniques in the 14 nm logic node and beyond is triple patterning lithography (TPL). Recently, LELECUT type TPL technology, where…”
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Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pair
Published in Proceedings of the 2003 Asia and South Pacific Design Automation Conference (21-01-2003)“…In this paper, we propose "selected sequence-pair" (SSP), a sequence-pair (seq-pair) with the limited number of subsequences called adjacent crosses. Its…”
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Conference Proceeding -
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Thermal Driven Module Placement Using Sequence-pair
Published in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (01-12-2006)“…TThe increase of power consumption in recent VLSI chip has led to uneven thermal distribution and high temperature on the chip. This brings inappropriate…”
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A fast algorithm for rectilinear block packing based on selected sequence-pair
Published in The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04 (2004)“…We propose a fast algorithm to obtain a rectilinear block packing in O((p+1)n) time keeping all the constrains imposed by a given SSP, a conventional method to…”
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Conference Proceeding